Hello,I am new to FPGAs and it is my first post here. We have developed a custom EP4SGX70 based board. FPGA Configuration is done using JTAG On the board we have EPCS64 which I am trying to use to store some custom data. MSEL[2:0] = 011 and EPCS64 is connected to the FPGA as per datasheets. I have build a test project in Quartus II and I am able to load in FPGA (using JTAG) and all runs fine. So I started testing the AMSI interface - I have added ASMI Parallel IP to my project and configured it for EPCS64 flash. - I have enabled read_sid feature as it looks as simple way to test if I can access the EPCS64. - In Quartus Assignments/Settings/Device/Device and Pin Options/ I have enabled "Active Serial (can use configuration device)" - I have provided 6.25MHz clock and reset to the ASMI IP and I have sent read_sid command (as per ASMI user guide) but I get 0xFF as Silicon ID. I do get busy signal with proper duration as per ASMI IP user manual. I hooked an oscilloscope at the pins of EPCS64 device and I measure the following: nCS - constant low DATA - constant high DCLK - constant low ASDI - constant low Note that above is after loading my FPGA configuration. What is puzzled me even more is that I measure the same voltages without ASMI IP in my project. it seems FPGA is keeping all SPI outputs low. (Something related with the fact we configure FPGA from JTAG? ) And I don't see any activity on the EPCS64 SPI bus (I put my read_sid in a 5 seconds loop) If I reset the FPGA board and before loading the FPGA configuration I have on SPI pins: nCS - constant high DATA - high impedance (I measure 0.7V) DCLK - constant low ASDI - constant high Probably someone can spot directly what I am missing? Or what can I do to investigate more? Thank you in advance! Dimitar
Hello,A small update. I have tested using single byte read command and still I get 0xFF from the ASMI Parallel IP data port, and still no activity on the EPCS64 SPI pins. What can I test more?
Your MSEL setting suggests you're ultimately going to configure the FPGA from the EPCS, in AS mode. Is that right? Have you tried this? This would at least prove the board. You can program the EPCS using JTAG Indirect Configuration (.jic), via the FPGA, if you don't have direct programming access to the EPCS.Have you constrained the I/O to connect all the pins, including the EPCS pins, as you require? You need to do this - don't assume Quartus knows simply because you've used an EPCS. An FPGA will happily support multiple EPCS devices connected to different sets of I/O, not just the config pins. It sounds like the ASMI IP is functioning but it's clearly not connected to the I/O you intend. Some FPGA's need you to specifically tell Quartus that you want access to an EPCS device, from the fabric, when it's connected to the FPGA's configuration pins (I don't recall specifically for Stratix IV). Check under 'Device and Pin Options' -> 'Dual-Purpose Pins'. Following a reset, with the board connected as you describe, you should see nCS assert (LOW) and DCLK toggling as the FPGA attempts to configure from the EPCS. You suggest 'DCLK - constant low' and nCS deasserted. This doesn't sound right to me. However, you say you can configure the FPGA via JTAG. This setup and these observations don't stack up. Cheers, Alex
Hi Alex,Thank you very much for your response. Indeed I am very new to Altera FPGAs so I guess I am doing something stupid. :) MSEL is indeed configured for AS mode. That was our initial intention. However we are able to program the FPGA from the PC thru FTDI FT4232H emulating the JTAG. Our board is always connected to a PC and on each board boot we load teh configuration from a PC and this method is convenient for us now. I have not constrained the EPCS pins! I have assumed that those pins are special as I didn't manage to find anything about those pins in the IP parameter Editor for the "Altera ASMI Parallel" block I guess here is the key. I will try to study the topic some more. Under 'Dual-Purpose Pins' I have two groups Data and Data[7..1] both set to "Use as regular I/O" , so I guess I am OK here. Thank you once again. Dimitar
Hello Again,I think I made small progress I have noticed the option in ASMI Parallel "Disable dedicated Active Serial interface" which makes my ASMI block explicitly route out the SPCS64 'SPI' signals So I routed those signals out to my top level and I have specified constrains in my qsf file to their actual pin location. One of the assignment is asmi_dataout to Pin_P26 Now the actual issue is that I get Error (176310): Can't place multiple pins assigned to pin location Pin_P26 (IOPAD_X0_Y44_N62) Info (176311): Pin asmi_dataout is assigned to pin location Pin_P26 (IOPAD_X0_Y44_N62) Info (176311): Pin ~ALTERA_DATA0~ is assigned to pin location Pin_P26 (IOPAD_X0_Y44_N62) If seems a dedicated pin ALTERA_DATA0 is already assigned to Pin_P26. I have tried all I could in: Device and Pin Options -> Configuration/"Dual Purpose Pins" but this error stays constant at my Fitter stage. The only thing I find in my qsf file about DATA0 is set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "COMPILER CONFIGURED" which OI tried to comment but this line is always updated as per my settings in the "Dual Purpose Pins" If I disable the assignment asmi_dataout to Pin_P26 just to give it a try things become even more interesting to me Error (169094): Can't place pin asmi_dclk at location AM3 (PAD_256) because that location is a dedicated programming pin location Error (169094): Can't place pin asmi_scein at location AM2 (PAD_257) because that location is a dedicated programming pin location Error (169094): Can't place pin asmi_sdoin at location AM1 (PAD_258) because that location is a dedicated programming pin location So my other 3 assignment fails as well. Can I use the programming pins ASDO, NCSO, DCLK and DATA0 in user mode for my EP4SGX70? What I want is to use the EPCS64 FLASH for user data and not for FPGA configuration at all. It is interesting that if I don't enable "Disable dedicated Active Serial interface" in the ASMI IP the compilation is fine. I am getting out of ideas. How to solve this? Thank you Dimitar
Unfortunately, the answer here is not what you're looking for...Refer to Table 10–10: "dedicated configuration pins on the stratix iv device" on page 10-42 of chapter 10 - "configuration, design security, and remote system upgrades in stratix iv devices (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/stratix-iv/stx4_siv510...)" of the handbook. This shows which dedicate pins are available in user mode - see the relevant column. The Active serial configuration pins you've connected the EPCS device to are not available in user mode. So, you cannot store the user data you're hoping to in it. It's only available for device configuration. Stratix IV does support Remote System Upgrade which allows the FPGA to reprogram the EPCS. Read up from page 10-50 of the same doc. So, the FPGA can write (and therefore read from) an EPCS attached to these pins. Enable 'Remote' configuration mode in your project to allow access to the device. However, I don't expect this will allow you to freely read and write user data in the way you're hoping for. This is different on newer device families but not, unfortunately, Stratix IV. Cheers, Alex
Thank you Alex,OK as far as I understand I can use only DATA0 in user mode. Any non-volatile storage inside STRATIX IV for a few bytes? Just to make sure. I found nothing in the handbook I really hoped we will be able to solve this without board redesign. Best Regards Dimitar