I do not see where it says this is not allow (handbook, pin connection guidelines) but Quartus is not presenting LVDS as an option. The dedicated clock inputs have always supported LVDS in Altera FPGA even when the general IO pins in the bank did not.
You cannot use LVDS on 3.3V IO Bank. Please see Intel Cyclone 10 LP I/O Standards Voltage and Pin Support
#1 this is Cyclone 10 GX ... not LP.
-- even then, for LP the LVDS receivers in the emulated banks are receivers ... I'd expect dedicated clock inputs to support this.
This is Cyclone 10 GX and we are talking about the dedicated clock inputs. LVDS inputs are powered off of VCCPT which is 1.8V for all IO standards.
from the Handbook ...
126.96.36.199. Guideline: I/O Standards Supported for I/O PLL Reference Clock Input Pin
The I/O PLL reference clock (REFCLK) input pin supports the following I/O standards
• Single-ended I/O standards
Intel Cyclone 10 GX devices support Differential HSTL and Differential SSTL input
operation using LVDS input buffers. To support the electrical specifications of
Differential HSTL or Differential SSTL signaling, assign the LVDS I/O standard to the
REFCLK pin in the Intel Quartus Prime software.
I see differental HSTL/SSTL supported in the 3.3V banks. To use that it says to assign LVDS as the IO Std in Quartus.
Note that this is in regards to dedicated input clock reference pins. There is a difference versus data pins which are clearly not supported in Bank 2L.
my bad...you had that written as GX.
anyway, Cyclone 10 GX does not support 3.3V io bank. Did you mean 3.0V instead?
You are right, LVDS input are powered by VCCPT = 1.8V.
Are you saying that because the bank is powered by 3.0V, you cannot select LVDS as your dedicated clock inputs? when you change the VCCIO to 1.8V, it works? what error do you see? Could you paste the error message here.
This is the 3V IO Bank. LVDS does not show as an option on the dedicated clock inputs in the 3V bank. The handbook is not clear on dedicated clock io standard options.
The dedicated IO are unique versus other LVDS pins and LVDS is a common differential clock source. Prior Altera/IntelFPGA device families have supported LVDS clock inputs in non-LVDS banks.
I need clarification.
I understand your problem statement, and I have crosschecked it with the Pin Planner and pinout files.
For Cyclone 10 GX and Arria 10, the IO architecture works differently.
First, determine what IO standard you are using,
Example: You cannot place LVDS IO standard in a 3VIO bank.
For full list of what IO standard can place in which bank, you can refer to
how to know what bank is LVDS IO bank or 3V IO bank?
Bank 2L is 3V IO bank
Then once you assigned the IO standard to its bank, what VCCIO, VCCPT, VREF, VTT should be used?