As long as the design is written in VHDL/Verilog and do not use any MaxV specific IP, the code will work on Max10 FPGA. If you've used and MaxV Specific IP, you will have to upgrade them to the same or compatible IPs in Max10 .
To maintain the highest possible performance and reliability. You must also check the operating requirements described for both MaxV and Max10 devices.
Kindly refer below link for more information.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf - Max10 Operating Conditions (Page 4)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/max5_handbook.pdf - MaxV Operating Conditions (Page 49)