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seanw_skhms
New Contributor I
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Is it possible to configure Agilex-F P-Tile to have a PCIe Gen4 X4 EP port and a Gen4 X4 RP port?

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Hi,

The document of "Intel FPGA P-Tile Avalon Memory Mapped IP for PCI Express Design Example User Guide", ug-20268, page#3 shows the design example does not support the Gen4 X4 EP port. Is it limited by the design example coding or by the FPGA hardware?

In the section of " Root Port Deign Example" on page#14, it shows the Gen4 X4 RP port design has four bifurcation. Is it possible to have just one single Gen4 X4 RP port without multiple of bifurcation?  (I saw the Quartus Pro tool does not give user the option to set the number of PCIe RP port to 1.)

In our design, we need to have a PCIe Gen4 X4 EP port and a Gen4 X4 RP port. Is it doable by using the Agilex-F P-Tile?

Thanks,

Xiao

 

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seanw_skhms
New Contributor I
170 Views

Hi,

Thanks for the helps.

I misunderstood your words of "only assign". Actually you mean "only connect", which makes sense for me. I will try it soon, and right now I am struggling on generating the RP IP.

Thanks.

Xiao

View solution in original post

9 Replies
SengKok_L_Intel
Moderator
211 Views

Hi Xiao,


Both Avalon ST and Avalon MM interface are not supported Gen3/4 x 4 at the End Point. The PCIe Controllers X4 is only available in Root Port mode.   


Please refer to table 6 in the following link for the configuration modes supported by the P-Tile Avalon-MM IP for PCIe.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avmm.pdf


Regards -SK


seanw_skhms
New Contributor I
202 Views

Hi,

Thanks for the information. Dose it mean the two X4 cores in the P-Tile can not be configured into EP mode? Where is the limitation coming from?  It looks like this limitation is also applying for the PCIe Gen5 interface in later Agilex-I R-Tile?

The document shows the Quartus tool will support user to configure the "bifurcation mux" in future version. When will it be available?

I do not see the answer if it is possible to configure one core in EP mode and other one in RP mode? Since the Avalon-MM bridge is built in user fabric, it should not be a problem to support mixed EP and RP modes. 

Thanks,

Xiao

 

SengKok_L_Intel
Moderator
194 Views

Hi Xiao,


1) There is a hardware limitation in the x4 core where it does not enable for EP, this is the same for R-Tile. See table 12 below.

https://www.mouser.do/pdfDocs/ag-overview.pdf


2) The “bifurcation mux” in table 57 is supported in v20.2, there is a plan to update this document in the next release.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avmm.pdf


3) In a single P-Tile, it can only support either EP or RP. Both EP and RP are unable to configure in a single P Tile at the same time.


Regards -SK  


seanw_skhms
New Contributor I
190 Views

Got it. Interested in the "4 X4" configuration shown in the Table-57, mentioned in the answer-2.

In our design, we just want to active the X4 RP port on the lane#4-7 driven by the X16 core, and to disable the X4 RP ports connected to the other lanes (lanes#0-3 and lanes#8-15). Is it doable?  Especially, we want to disable the PHY on lane#0-3, when the X4 RP port on lane#4-7 is running. 

Thanks,

Xiao

SengKok_L_Intel
Moderator
185 Views

Hi Xiao,


It looks fine to me. You may start with a simple design and only assign the pin for port 4-7 and determine whether there is any abnormality from the Quartus compilation.


Regards -SK


seanw_skhms
New Contributor I
180 Views

Let me try it out later. But currently I stuck in generating the RP IP.

Does the routing tool consider it as an error for unassigned ports at lane#0-3 and lane#8-15?  Actually the PHY locations for these unused lanes are fixed and the pad location can be assigned automatically by the routing tool (other company's fpga tool does like this). I worry that the RP port on lane#0-3 could be active still?

Regards,

Xiao

SengKok_L_Intel
Moderator
174 Views

Hi Xiao,


Yes, can. You may leave the unuse port not connected. I did a quick compile by only connect either Port 0-3 or Port 4-7, there is no compilation error. And also, I did not do any pin assignment, the Quartus will help to place it to the right location.


Regards -SK


seanw_skhms
New Contributor I
171 Views

Hi,

Thanks for the helps.

I misunderstood your words of "only assign". Actually you mean "only connect", which makes sense for me. I will try it soon, and right now I am struggling on generating the RP IP.

Thanks.

Xiao

View solution in original post

SengKok_L_Intel
Moderator
162 Views

Hi Xiao,


If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


Regards -SK


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