Community
cancel
Showing results for 
Search instead for 
Did you mean: 
shvlad
Beginner
249 Views

Is it possible to create netlist for module which include one submodule like an RTL source?

For example, there is a tree:

-top_module

--submodule l1

---submodule l2

----submodule l3

-----submodule l4

---submodule l2

---submodule l2

--submodule l1

---submodule l2

 

I want to pack all hierarchy to one .qxp file except submodule l4, I want to leave it a source.

 

For example, submodule l4 include a chain of register, so users can change a length of the chain, but other design is closed for them.

 

Regards, Vlad.

0 Kudos
7 Replies
sstrell
Honored Contributor II
106 Views

If you set l4 as a design partition, you can use the root partition reuse flow documented here:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-block-based-desig...

 

You're basically locking down the I/O design and including all the other submodules in the root partition along with the I/O, leaving l4 as a "doughnut hole" in the middle. You then reuse the root partition with all the other submodules and put whatever you want in l4.

 

#iwork4intel

shvlad
Beginner
106 Views

It works! Thank you!

shvlad
Beginner
106 Views

I think I was happy too early.

My approach worked when I use first level submodule, but when I put it deeper, I faced problems. 

I used to ways

1. Empty partition for Blackbox module was created in main netlist project. Root partition with Empty subpartition for main netlist project was exported. exported partition was imported in another project. Now I faced the error "Error (35013): Found unexpected partition in previously generated netlist with no corresponding partition definition in the current project" within partition merge. 

2. I didn't create partition for submodule (instantiated like a black box), I created only root one. The partition was imported to another project successfully. But I added source instead black box, but it not affects to design. 

 

Unfortunately, almost all info about such tasks are for Quartus Pro, but I use Standard edition.

 

BR, Vlad.

shvlad
Beginner
106 Views

I attached two .qar archive with the Quartus project.

"top heartbeat" is design which supposed to be netlist (with the unencrypted source cnt_l2)

"top" is design which supposed to use "top_heartbeat" like a netlist. Source "cnt_l2" must be changible in top project.

 

In the example i represented "way 2" from last post. To check "way 1" please execute "set as Design Partition"->Netlist type Empty->Export Design Partition for "top_heartbeat" project. New .qxp include to "top" projct. In such case I catch error.

 

Regards, Vlad

shvlad
Beginner
106 Views

Second archive

106 Views

You can refer to the document below for creating a design partition. This is based on Quartus standard edition.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-compiler.pdf

106 Views

I checked and don't think it is possible to create netlist for module which include one submodule like an RTL source, as the qxp is in the top already. you cannot have a submodule with a source in it. 

Reply