Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Is the extreme error on the TSD of the MAX10 CPLD actually a hardware issue?

CPelk1
Beginner
‎09-23-2019 01:44 PM
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In the link attached there is a note saying that there is a bug in the ADC IP that makes the TSD error outside the tolerance band and that it would be fixed with later versions of Quartus. However, I saw this problem on Quartus 16.1 (which is a later version than what this post was referencing) and after downloading and testing Quartus 18.1. Either the software bug hasn't been fixed or this is actually a hardware issue. Can I get some insight here? Thanks.

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Rahul_S_Intel1
Employee
‎09-24-2019 07:55 AM
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Hi ,

I just gone through internal documents, the issue is fixed that is what I come to know.

 

It is not hardware issue.

 

 

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