Feed the pulse into an asynchronous SR latch 'S' input such that the presence of the pulse will put the latch into the SET state. Note the pulse must be at least long enough (two gate delays) to allow the SR latch to go to the SET state.
Then feed the output of that asynchronous SR latch into a dual rank clocked synchronizer. Now your signal will be in the clock domain as a synchronous signal, and you can use it in logic as desired.
The synchronized output should remain set until you go and generate a clear/reset signal and feed it into the 'R' input of the above SR latch, to put it back into the state of 'looking' for the next async pulse.
This scheme requires that the input pulse have a minimum pulse width (as mentioned above) to reliably set the input latch, and that the time between pulses be long enough to synchronize the pulse to your target clock signal, process it, and then reset the input latch back to pulse recognizer mode. If the time between pulses is too short, you will end up missing the subsequent pulses while processing is active.
Alternatively, if the pulse meets the minimum clock pulse width requirement for a register, feed the pulse into the clock input of the register, and supply a logic high to the data input. Connect the output of the register to the dual rank synchronizer input, as was done above using the SR latch. Connect the feedback clear signal to the async reset input of the register to re-enable it to detect the next input pulse.
