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TNguy162
Beginner
354 Views

Issue of using F2H bridge on Arria 10 to access H2F_LW.

Hi everyone,

I have an issue related to using F2H bridge to access registers on FPGA via H2F_LW bridge.

As I read from the Arria 10 HPS technical reference manual, from the address table of page 378, I thought that F2H bridge can access to slaves of H2F_LW from address 0xFF200000 to 0xFF400000. Is this right?

arria10_address.jpg

When I send a read or write command to this address area, I found that there is no command on H2F_LW. Maybe my command was blocked somewhere by HPS. HPS did not forward my commands to H2F_LW as I want it to do. Do I need any setting for H2F_LW bridge? Or any setting on HPS that I need before sending commands?

 

Any advice is highly appreciated.

Thank you.

 

Best Regards,

Joe

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12 Replies
69 Views

Hi Joe,

 

I would recommend that you check our Arria 10 HPS-to-FPGA device guidelines:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-device-design...

 

 

69 Views

Hi,

 

Do you have any more question?

TNguy162
Beginner
69 Views

Hi el.ign,

Sorry for a late reply.

I read the device guidelines but I cannot find the reason why I cannot send a command from f2h bridge to h2f_lightweight since we have the address as the above picture.

We changed our design and don't use f2h bridge anymore.

Thanks for your information.

 

Best Regards,

Joe

69 Views

Hi Joe,

 

Thanks for the follow up.

 

Based on my knowledge, the h2f_lightweight are intended for control or status registers, there will be an issue when is used for other usage.

 

Best Regards.

 

 

TNguy162
Beginner
69 Views

Hi el.ign,

 

Thanks for your information.

We used it for accessing status register too. However, we used F2H bridge to forward the data to h2f_lw to write to status registers. Somehow it does not work.

Anyway, we changed the design and it's ok now.

Thanks for your help.

 

By the way, this is another issue. If I have APB interface working at 100MHz clock domain and it writes to registers working at 250MHz clock domain. I need to handle these two clock domains so I used another APB interface which has 250MHz clock and put it in between the APB-100MHz and registers. I found that Platform Designer inserts clock crossing adapter between APB-100MHz and APB-250MHz. I don't know whether if it is safe to let Platform Designer insert Clock crossing adapter or we should handle manually. What is the best practice in this case? Would you please share some experiences or share some documents about this issue? I appreciate your help.

 

Thank you so much.

Best Regards,

Joe

69 Views

Hi Joe,

 

I am not that familiar with the clock crossing that you mentioned. I believed if the Platform Designer automated the adapter, it should be fine because of the two different clock domain frequencies.

 

Was there any issue with the adapter so far?

 

 

TNguy162
Beginner
69 Views

Hi el.ign,

 

Thanks for your reply.

I think the same. We ran simulation and tested on board. There is no problem so far but I'm just worried about meta-stability. That happens occasionally and hard to detect on board.

 

Best regards,

Joe

69 Views

Hi Joe,

 

Let me check for any information I could find and check with out internal team regarding this.

 

Best Regards.

TNguy162
Beginner
69 Views

Hi el.ign,

 

Fantastic!! I appreciate that.

 

Best regards,

Joe

69 Views

Hi Joe,

 

No problem, Ill update once I got the reply.

 

Thanks

69 Views

Hi,

 

The automated by the Platform Designer are fine.

 

though if happens any error, do not hesitate to file a new case.

 

Thanks!

TNguy162
Beginner
69 Views

Hi,

 

Thank you very much.

 

We have no problem so far.

 

Cheers,

Joe