It may sound naive.. Is there any good open source FPGA design? for education purpose

[Altera_Forum]

Hello 

 I've been trying to learn some designing HW by FPGA verilog.   My background is, I have experience about building customized PIO using DE1-SoC, hashing support HW,, and not much.   I think it is enough for 'playing' with FPGA, and I want to enhance my skill.  What I'm trying to look is, well coded open source verilog FPGA design, so that I can learn some skill and idea from it.  Let me give you an example,    someone told me about learning C language,   " it is better strategy to learn coding by analyzing well coded program, such as Linux kernel, than practicing building program by yourself, because your thought is limited so your coding skill will not improve that much "   well I think this is very true because as I look inside the linux kernel source, specifically strat_kernel(), what I found is such a beautiful logic inside of it .. this doesn't tell me 'the programming skill' directly, but somehow I learned some idea from it, something like manipulating struct data structure for example.  Anyway, I'm trying to look well coded open source verilog FPGA design, so I can learn some idea, as same as linux kernel in C. Of course not that much as sophisticated as linux kernel, but I want any reference design to learn.  It would be really appreciated for any helps..   Thanks in advance,!!! : D

[Altera_Forum]

"Well Coded" and "open source" dont usually go together in FPGA land. Most open source projects are hobby projects which generally lack documentation or good coding practice (IMO) 

Open source cores can be found at opencores.org.  Another source of learning will be reference designed supplied by Altera and Xilinx (for their FPGAs).

[Altera_Forum]

I see 

 well I am quite newbie in FPGA land so I have little idea of this field work.. (that why I added naive in title of this thread)  Can I ask you one question??  what would be the general parameter for good FPGA design ?? so that I can practice building my design to fit the good parameters as possible.   for example, when I practice building FSM, I heard that one hot encoding, (make FSM state have only one bit set) make 'lower' the complexity of HW.  I believe less complex HW is obviously good design. So I thought complexity is one of the parameters.. yet I'm not sure exactly what complexity is though .  So could you tell me any idea of good design ?? generally ?? in HW perspective  Thank for your help !!!!   ps : wow you are Forum Master .. impressive (o 0 o)

[Altera_Forum]

A good design is one that works that meets the specifications. Specifications and requirements will vary by project, so its impossible to define good paramters. 

When writing code - you should ensure that it is easy to read and well documented/commented. Comments should be more about "why" rather than "how", as the latter will be explained with the code (obviously helpful notes should be placed to guide others through the code).  Your example about FSM is pretty superfluous. Design the FSM in your code to be easily readible. Let the synthesiser take care of the encoding.  Make sure you follow good design practice (fully synchronous design, good clock domain crossing techniques etc) and your designs will need less debug on hardware.  And also - make sure you get into the habit of simulating your code. Well simulated and tested code will require less debugging on the bench, which is far more painful and slower than in a simulation testbench.

[Altera_Forum]

The short answer is that there is not any equivalent to the Linux kernel, and there is not anything publicly available that people point to as a gold standard for HDL techniques. 

 You probably won't learn much without picking a specific objective or application domain (networking, video, storage, ... ) and trying to write something yourself. And then for guidance, fall back to traditional methods such as books and papers.

[Altera_Forum]

Thanks Mr Tricky. 

 I will remember your advice.. thank you very much.  And one last question .. this is kind of question that is not relative to this topic though,  I heard that some scholars say, Not too far, there will be the era that auto-hardware synthesizer will be invented.  The idea is this, compiler will be able to know which part of software program can be executed fast or better if that part is done by HW, such as matrix calculation or large computation.  So compiler can generate HW to support software program by itself, which leads to the demand of HW design by human can be decreased..  I'd like to know your opinion about this, does that scholar's saying sound probable to you ??   Thanks in advance.. for your kindness of answering to my silly question..

[Altera_Forum]

Mr ted. 

 Well,, I cannot agree more of your opinion that I should pick some domain to apply! ..  thank you

[Altera_Forum]

--- Quote Start ---   I heard that some scholars say, Not too far, there will be the era that auto-hardware synthesizer will be invented.  The idea is this, compiler will be able to know which part of software program can be executed fast or better if that part is done by HW, such as matrix calculation or large computation.  So compiler can generate HW to support software program by itself, which leads to the demand of HW design by human can be decreased..  I'd like to know your opinion about this, does that scholar's saying sound probable to you ??   --- Quote End ---    It will probably happen at some point, and will be helped by Intel owning Altera. But we are still a long way off. C to gates has been around for 20 or so years, but it's still no where near the efficiency of pure HDL. Modern Things like OpenCL, HDL Coder and simulink bring more people from the software world into FPGAs and make the transistion easier. It also allows rapid prototyping. But when Costs savings and logic reduction is required, nothing beats pure HDL.