We have ported the JAM player onto an embedded processor. I can see the status is JBIC_SUCESS but the exit code says Device programming Failure. The FPGA is a MAX10 (10M08SC169I7G) device and it can be programmed using the byte blaster.
What would be the reason to get an exit code of 10?
I found a similar case as yours in forum community.
Please take a look and see if it can help.
I can the exit code 10 is set in case 0x25
case 0x25: /* EXIT */
*exit_code = (int) stack[--stack_ptr];
done = 1;
How or why it gets here is harder to find out as the stack array is modified in many of the case statements which go to 0x80
So do you still have issue with the exit code?
Perhaps you can refer to AN425 on using JAM STAPL.
I checked the page 5 you mentioned.
I have also attached the options I saw from the programmer when generating the jam file. The ISP clamp is turned off by default and I checked to make sure the ISP option is unchecked in the programmer options. I have attached the screen shots below.
It is not clear for me how to disable the ISP option. We have an MCU which is used to program the MAX 10 on the board. The JAM player is ported to that MCU to run the update.
Do I change the ISP mode from a quartus option in the .jam file generation or do i need to change anything in the jam player to send that command? For eg: in the jbi_execute function?
Thanks in advance for your help.
Apologize that previous reply does not help to solve this.
Just to confirm, you are already using Quartus programmer to programmer .jbc or .jam files is it?
Have you try to use quartus_jli command-line to program .jbc or .jam files? You can refer to page 10 of the AN425
I would describe my setup once again.
As I mentioned in previous posts, we are not using JAM player from the pc.
We are using JAM player from an embedded MCU.
To load program from quartus, we use the .pof file with the programmer and USB blaster II
The program is ported to the embedded target and we have four pins connected to the MAX10 to program the FPGA.
After you shared the tip about the ISP option, I tried two options:
1. Disabled the ISP and generated the JAM file and converted it to a hex file and used it to program the FPGA.
I get the exit code 10 as mentioned before. The image in fpga is unaffected.
2. Enabled the ISP and used the generated the JAM file to program the FPGA. I got exit code 0!! from both Program and Verify action.
After power cycling though, I saw the FPGA logic is absent and it is at the reset state.
So did the above option just erase the flash? In that case, why would I get successful programming confirmation from JAM player?
Or do I need to try something else to transfer the logic to SRAM if I use the ISP option?
Is there any other options I can try? I can recreate the ISP situation I described above.
If I disable ISP, I get exit_code 10 and device program in CFM is unchanged.
If ISP is enabled, I get exit_code 0 but it erases the CFM.
We are using 10M08SCU169A7G device and JTAGEN is disabled. So the JTAG pins are reserved for JTAG alone.
Apologize for the delay in response.
- Can you show me how did you generate the JAM? Show the setting when generating this file.
- Can you share the picture on how you do the programming?
Apologies for the delayed response. I had some access issues to the community forum.
I have attached the settings. The Max 10 JTAG chain is connected to GPIO of our embedded mcu. We ported the jam player to the cpu.
We generate the JAM file and then convert the JAM file to JBC format using the jbc.exe using
"jbc -f2 -u xxx.jam xxx.jbc"
Are the above options correct to use? We convert the jbc file to a C file with the entire buffer.
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