error: jtag id code specified in jedec stapl format file does not match any valid jtag id for device. Hi everyone! I've been trying to have my FPGA programmed, but it doesn't work :( The error above occurs when I click on start button of the programmer. I am using Quartus II version 9.1 (have already tried version 10 as well - I get the same problem). Also, when I test "JTAG Chain", I get the following message: "error: unknown integrity checking failure". My device is EPM7128SLC84-15 I've been looking for a solution through Google, but couldn't find anything yet. I'd appreciate your help! I'm running out of ideas of what to do... Thanks, in advance! Regards, P. Nallin
Had this exact same problem. Here is what I did to correct it. I put a 1K Ohm resistor from TCK to Ground.===========altera questions =========== q:should tck be pulled up or down? a:Since 2000, Altera devices have been designed for a pull DOWN resistor on TCK for both 3.3 and 5V devices. (Most non-Altera devices tend to expect a Pull UP resistor on TCK) Source: http :// www .ricreations. com/boundary-scan-faqs.html#altera_questions (sorry about the formatting, new users can't post links/images, will correct this when I am more human.) OP stated his/her device was a "EPM7128SLC84-15" - FPGA, but I am pretty sure its a CPLD, but what do I know, I am not human, yet.
Hi ,Error: Can't configure device. Expected JTAG ID code 0x020A20DD for device 1, but found JTAG ID code 0x070640DD Error cam during download. ???? Naveen