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JTAG scan chain broken

Vasudev
Beginner
276 Views

Hi,

 

I'm trying to program a standalone Cyclone III FPGA (EP3C10E144C7) using the USB Blaster II cable in the JTAG mode. I load my FPGA into an adapter that breaks out the 144 pins of the FPGA into DIP pin headers which are connected appropriately. I have provided all the voltages (VCCINT, VCCIO_x, VCCAx, VCCD_PLLx, VREFBx) according to the recommended values. I have also followed the "JTAG Configuration" section in Chapter 9 of the Cyclone III device handbook vol. 1 to program the FPGA using JTAG. 

 

I use Quartus II 64-bit version 13.1.4 on my Windows 10 laptop. However, when I try to "Auto Detect" the JTAG chain from the Quartus II Programmer, I get a message saying that the JTAG chain was not detected. In the JTAG debugger in Quartus II Programmer, when I perform the Integrity test, it fails with the error "JTAG scan chain broken". Running "jtagconfig -d" from the CMD prompt is no help either - it provides no additional information apart from "JTAG chain broken". 

 

To investigate further, I checked the TDI, TCK, TMS, and TDO signals on an oscilloscope. The TDI, TCK, and TMS signals seem to be functioning correctly, but something seems to be wrong with the TDO signal. When I execute the integrity check from my laptop, the TDI, TCK, and TMS signals respond, but the TDO signal seems to be responding very faintly. Its amplitude is extremely low (~50mV) compared to the other signals (2.5V). I believe that this is the reason why the USB Blaster II is not able to detect it and hence the "JTAG chain broken" error. 

 

I tried to increase the drive strength of the TDO pin in the Pin Assignment editor in Quartus II, but since it is a programming pin, I can not make any changes to it. 

 

I would really appreciate it if anyone could help me fix this issue.

 

Thanks in advance,

Vasudev

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5 Replies
Ash_R_Intel
Employee
256 Views

Hi,


Please check the pad connections on the board. There is a possibility that due to weak soldering, the signal is not getting driven properly.


Regards.


Vasudev
Beginner
233 Views

Hi,

 

Thanks for the response. I checked the connection on the board. It seems to be fine. On applying 2.5V at the DIP header on the board, I get 2.5V inside the adapter (where the FPGA pin is connected). 

 

I forgot to add this in my original question: The device package has an exposed pad at the bottom. I do not connect it to any pin. Does it absolutely need to be connected to GND or is it okay if I do not connect it?

 

Regards,

Vasudev

Ash_R_Intel
Employee
203 Views

Hi,

Please refer this handbook: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii51015.pdf

Page 1 has this info: "All E144 packages have an exposed pad at the bottom of the package. This exposed pad represents the ground pad that must be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity and not for thermal purposes."


Regards.



Vasudev
Beginner
192 Views

Hello,

 

Thanks for pointing it out! I'll have to drill a hole in my PCB or solder it using a very thin wire to make this connection so it will take some time. But I'll let you know how it goes.

 

Thanks with regards,

Vasudev

Ash_R_Intel
Employee
170 Views

Hi,

Hope the issue is resolved. Closing this case.


Regards.


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