Jtag signal integrity program

Altera_Forum · ‎07-26-2011

Hi all:

I have develop a custom board of stratix iv gx, with jtag and AS configuration. I find:

1) One week before, I can debug the fpga through jtag with USB-blaster cable(Rev C), and configurate epcs64 with USB-blaster cable too;

2) Now I add a chip with about 10 watt on the board, then I can't debug the fpga through jtag and configurate epcs64 with USB-blaster cable, but when I use Byte-blaster II cable, jtag and configuration are ok;

I searched the forum, someone said this may result by TCK or other jtag signal integrity, and can be solved by good wiring. But I had develop some custom boards with different fpga(cyclone, cyclone II, Stratix II, Stratix II GX,ect), every board is ok when I test and configurate with byte-blaster II cable, but the USB-blaster cable didn't work.

So I want to know that is it correct of JTAG Schematic for USB-blaster cable? Because I find that there is pullup resistor for TDO, series capacity and resistor for tck in some develop board, but there isn't these Elements in fpga datasheet.

Can anyone give me a good answers?

Thanks.

Altera_Forum · ‎07-28-2011

I solved the problem by change some decouple capacity of VCCPGM pin.But I have found it can't configurate sucessfully if TDO have no pullup resistor.

Altera_Forum · ‎07-29-2011

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I solved the problem by change some decouple capacity of VCCPGM pin.But I have found it can't configurate sucessfully if TDO have no pullup resistor.

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Could u share the change things here?

Thanks

Jerry

Altera_Forum · ‎08-11-2011

I change some capacity value from 0.01uf or more less to 0.1uf.