Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

LPC controller

Altera_Forum
Honored Contributor II
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Hi, 

 

Do Altera FPGAs support LPC (Low Pin Count) controller as soft-IP core? I couldnt find it. I am having to design a system where a CPU interacts with the FPGA through the LPC bus apart from PCIe. 

 

Or would I have to code my own controller? 

 

Thanks, 

Satish
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

Do Altera FPGAs support LPC (Low Pin Count) controller as soft-IP core? I couldnt find it. I am having to design a system where a CPU interacts with the FPGA through the LPC bus apart from PCIe. 

 

Or would I have to code my own controller? 

 

--- Quote End ---  

 

 

I don't recall seeing one from Altera. Have you tried looking at opencores.org

 

I vaguely recall looking at the LPC interface and it didn't look too hard to code a controller for it. If opencores does not have anything you want to use, code up an interface, and a bus functional model, and if you have trouble, post the code here.  

 

Note that if you post code with a Modelsim testbench you're more likely to get a response :) 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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Thanks very much for the confirmation. 

 

I would look for it in open cores, else sit down to code one myself. 

 

Regards, 

Satish
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Altera_Forum
Honored Contributor II
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I want help about Lpc bus controller, I want to connect my FPGA throw lpc to Motherboard(lpc host ) ,I want to use only Firmware memory and Firmware memory write Cycles.I see Lattice document but I can't find any verilog code , please help me. 

thank you.
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Altera_Forum
Honored Contributor II
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The source code for the Lattice controller is licensed only for use on Lattice devices. 

 

You'll probably have better luck with the OpenCores one as a starting point. 

http://opencores.org/project,wb_lpc
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

The source code for the Lattice controller is licensed only for use on Lattice devices. 

 

You'll probably have better luck with the OpenCores one as a starting point. 

http://opencores.org/project,wb_lpc 

--- Quote End ---  

 

 

yes thank you, but it is Wishbone LPC , what is wishbone? 

I know only principal of LPC signaling and protocol,please help me more about that.
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Altera_Forum
Honored Contributor II
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Wishbone is described here. http://opencores.org/project,wishbone,wishbone 

 

If you don't want to use it, you would remove it and replace it with something else (Avalon-MM, ...)
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