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Altera_Forum
Honored Contributor I
798 Views

LPM Divider execution time

What is the maximum time to perform a division with Altera LPM_DIVIDE without clock (only combination divider). I am using only unsigned integers and I don't care about the remainder. The numerator is 13 bits and the denominator 8 bits. I am using an EP4CE22F17C6N. 

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Altera_Forum
Honored Contributor I
46 Views

There is no "time". If you go without a clock then the propgation delay will be affected by PVT (process, voltage, temperature) and routing meaning every time you compile it the prop delay will be different. And to top it all off, you have no idea how long it takes before it would be stable as there is no way to measure it. 

 

With a clock, you can measure all these things and you know the "turnaround" time. And to top things off, the higher the pipeline delay, the faster the clock speed you can achieve.
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

There is no "time". If you go without a clock then the propgation delay will be affected by PVT (process, voltage, temperature) and routing meaning every time you compile it the prop delay will be different. And to top it all off, you have no idea how long it takes before it would be stable as there is no way to measure it. 

 

With a clock, you can measure all these things and you know the "turnaround" time. And to top things off, the higher the pipeline delay, the faster the clock speed you can achieve. 

--- Quote End ---  

 

 

My system clock is 3MHz, that means to have a result in one system clock cycle can i use I higher clk (for example 10Mhz) for the divider with pipeline?
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

My system clock is 3MHz, that means to have a result in one system clock cycle can i use I higher clk (for example 10Mhz) for the divider with pipeline? 

--- Quote End ---  

 

 

No, it does not mean that. You need to run the timing analysis to see if your circuit will work in the way you've configured it. 

But at 3Mhz, the divider will probably meet timing with a pipeline length of 1.
Altera_Forum
Honored Contributor I
46 Views

Still the clock for the divider has to be greater (at least double) than system clock right?

Altera_Forum
Honored Contributor I
46 Views

No, the clock for the divider should be the system clock, otherwise you'll have all sorts of timing problems to overcome. 

What is wrong with a pipelined multiplier?
Altera_Forum
Honored Contributor I
46 Views

What do you mean with pipelined multiplier?

Altera_Forum
Honored Contributor I
46 Views

I meant to say pipelined divider.

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