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Hello,
today I upgraded to altera V12.1-177. I created a new LPM SHIFTREG block with a load pin and a clock pin. The block has an 8-bit bus input and an 8 bit bus output. That being said I have tried I introducing an 8 bit byte at the input and and the byte can be seen at the output. However, the block ignores any input signal at the load pin. Dido if I use a clock enable. it seems the block does not pay attention to any control lines such as the load, clk enable or clocks??? anyone else experiencing this? rLink Copied
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