LVDS Links bet. Cyclone and Cyclone III

[Altera_Forum]

Hi,  

 Thanks in advance for reading this query.    I am designing a board to link a Cyclone (on one product with limited pins available) and a Cyclone III evaluation kits. Need your kind advice for these:   1) For simplex comm, Tx at Cyclone - Rx at CIII, a general purpose differential channel can be used to transmit ext. clk to CIII. Must we use the dedicated clock channel at CIII?   2) For duplex comm. bet. Cyclone and CIII, a PLL can be shared between transmitter and receiver in either side. i.e. at Cyclone, one PLL takes one input clk (e.g. Cyclone ref. clk) and generate two output clks to drive tx (fast and slow clk), and one ext clk for CIII. How to handle ext clk from CIII in Cyclone?     Thanks.   Y.Z. Liu

[Altera_Forum]

Using non-dedicated pins for clock output introduces additional skew and some jitter. In most cases, it should be acceptable. 

 When a LVDS receiver is operated source-synchronous with an external supplied clock, the receiver PLL must be driven from this clock. Sharing the PLL means clocking the transmitter from the external clock, too. This can work only at one side of the link and involves additional jitter for the TX clock and data, which is most likely unwanted.

[Altera_Forum]

--- Quote Start ---   When a LVDS receiver is operated source-synchronous with an external supplied clock, the receiver PLL must be driven from this clock. Sharing the PLL means clocking the transmitter from the external clock, too. This can work only at one side of the link and involves additional jitter for the TX clock and data, which is most likely unwanted.  --- Quote End ---     Thanks a lot.   LVDS receiver must operated in source-synchronous mode, unless soft CDR mode is supported by the device, isn't it?