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Altera_Forum
Honored Contributor I
1,313 Views

LVDS critical warning

hello 

 

I got many warnings which are ... 

"ID:12887 Too many 2.5-V SE IO in bank <name> with LVDS RX pin <name>. Reduce the number of 2.5-V I/Os used and re-run the analysis again. ...." 

 

and I am told its solution that "Reduce the number of SE IOs". 

 

I have some questions about this. 

 

1. what is SE IOs 

actually I'm just told SE. 

what is it? 

 

2.what happens? 

since those are warnings, I got sof file. 

what will be happened if I use this? 

 

3.any solution. 

there is not plenty of space for removing pins 

what can I do then? 

should I change FPGA? 

 

thanks in advance.
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3 Replies
Altera_Forum
Honored Contributor I
41 Views

SE = single-ended. There must be rules for your target device about how many single-ended IOs you can have in your LVDS banks (usually only SE outputs matter). There are sometimes proximity rules as well that are errors instead of warnings and the tools won't let you compile the design. In those cases there are usually .qsf constraints that can bypass the errors, but then it's on you to live with the consequences. 

 

If your single-ended outputs don't transition much then you may be fine, but if they are extremely active outputs you might want to be more conservative and try to abide by the rules.
Altera_Forum
Honored Contributor I
41 Views

thanks rsefton. 

 

if it is only SE outputs matter. 

can I ignore those warning , if whole LVDSes are only inputs.
Altera_Forum
Honored Contributor I
41 Views

If you search on that warning in the knowledge base you'll find this: 

 

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10102013_979.html 

 

Read this and follow the links and it should explain what you need to do.