LVDS in Stratix II / Cyclone II – Do I have to use 2.5V?

[Altera_Forum]

Stratix II and Cyclone II require 2.5V for the VCCIO if I use LVDS. I only need a couple of LVDS input pins, but all of my other I/O require 3.3V LVTTL. How can I avoid using 2.5V on an entire bank for a couple of LVDS inputs? Do I have to use an external buffer?

[Altera_Forum]

No, you don’t need an external buffer if you only need a small amount of LVDS inputs. On Cyclone II you can use the dedicated clock input pins. They use VCCINT, not VCCIO to power LVDS input buffers. On Stratix II, use the top / bottom bank dedicated clock input pins. Those are powered by VCCINT, not VCCIO as well when used as LVDS inputs. Same for differential LVPECL.