Large cloth path delay, how to resolve?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Large cloth path delay, how to resolve?

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Using an Arria V device and use an ALTPLL to connect a pin input reference clock and generate internal clocks.

TimeQuest reported timing (setup) violations.

The LOL is very small, clock period is 10, clock path delay is 7.5, some cells on the data path has an incr of 4.5 and 5.5!

is the clock tree not balanced? some nodes are placed too far away? any idea how to fix this issue?

Thanks a million.

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