Latching asynchronous signal

[Altera_Forum]

Hi, 

 I need to design a circuit for latching an asynchronous signal and later I need to do some processing on this signal. I am planning to use double registering of the signal before its used for processing.  Are there any specialized sync D-Flip flops to do this or just the normal flip flops would do the job? I am using Arria V FPGA, VHDL language.  Thanks

[Altera_Forum]

Normal flip flops will do it, but if it's coming from an external source, you'll want to make sure it uses the fast IO registers in the IO pin. (this should be done automatically but you can force it via assignments or attributes)

[Altera_Forum]

My guess is that the tool would not like io register as it wants the two flips to be as close as possible to reduce MTBF. So I assume a pair of fabric registers would be chosen. io registers are not in pairs and the external delay of async input is irrelevant.