Latency of DE0-nano ADC

[3df]

Hi, everyone,

I am trying to use a DE0-nano for an application (I'm a beginner) and I was checking its ADC latency. I built a circuit that; in summary, reads the ADC value and echoes the binary code in another digital pin. The setup is running the ADC I2C with a 2.3MHz clock and is based off this code: https://github.com/stffrdhrn/adc_interface

My hope is that this could eventually be used for a closed-loop real time controller.

I was able to make the Verilog code work and output sensible values, but I'm a little concerned about the latency. I attached a picture of a measurement; in Channel 1 I have the square wave going from the value where the ADC reads 0 (it's about -0.25 V) to an arbitrary value (about 1.8V). as you can see, the FPGA piped output reads zero for a really long time, approximately 732us as measured by the scope cursors. It was so much delay that I had to lower the frequency of the wave all the way down to 60Hz to see the delay!

I know this is not really the FPGA's fault, but I'm rather impressed by the amount of latency. Is that normal for ADCs? Or is there something I'm doing potentially incorrectly?

Thanks!

[WZ2]

I did a quick check of the code. Since it's not using an on-chip ADC, the delay is unpredictable due to data transmission and communication overhead. If you want to accurately measure how fast the FPGA processes data internally, you can add SignalTap probes at the data input and output points and calculate the internal processing latency.

[FvM]

Hi,
to know about ADC128S022 latency, read the datasheet. You'll find that it's below 5 us at 3.2 MHz clock frequency and single channel operation. Everything else is software overhead.