Limit PCIe speed to Gen2

[emrahener]

Hi,

I am using Multi Channel DMA Intel® FPGA IP for PCI Express IP on a Agilex device to implement a x16 PCIe EndPoint.  Due to some problems I want to change the advertised speed to Gen2 form Gen3. IP parameters does not allow me to do so. Is there a way to do so ?

Quartus Version :23.1

DEVICE :AGIB027R31B2E2VAA

Kind Regards,

Emrah ENER

[Wincent_Altera]

Hi,

Can what IP parameter does not allow you to do so ?

My suggestion is regenerate a new design example for pcie gen3.

Is any printscreen that you can show to me ?

Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[emrahener]

Hi Wincent ,

Screen shots is below. We are using MCDMA PCIe IP  As you can see there is no Gen2 option. We want to limit our HW capability to Gen2 and don't want our endpoint to negotiate up to Gen3 speed. I also attached the speed options for streaming version which also don't have any Gen2 option.

MCDA IP

Streaming IP

[Wincent_Altera]

Hi,

You can generate the gen3 design example. But please ensure that you set your BIOS PCIe speed setting into gen2.

Then suppose it will auto downgrade into the gen2 speed.

You may check the gen speed via

$ sudo lspci -s 01:00.0 -vv

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[emrahener]

Hi,

Down training is a capability  which every PCIe endpoint must support. My question was related to limiting end point capability to Gen2 (Inside MCDMA PCIe IP) not limiting it from PCIe switch side. Can you please confirm that this is not possible through IP parameters or through modifying generated ip hdl files?

[FvM]

Hi,
I'm pretty sure that you can achieve what you want by modifying generated IP files. The feature to limit the maximal speed of a PCIe design has a different purpose, it's there to reduce the interface clock speed or bitwidth when you don't need it. For some reason, the Agilex Gen 4 IP has no feature to configure for below Gen 3 speed. It's probably a matter of reducing the number of alternative core configuration.
If you step through the PCIe simulation, you'll see that communication really starts at Gen 1 speed, going up to the maximal speed supported by both peer. I guess you can simply reduce the advertised speed, but I didn't look into the details.
Regards,
Frank

[Wincent_Altera]

Hi,

if according to the user guide if Agilex I-series.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_ptile_pcie_avst-20-3-3-1-0.pdf

under page 6/203

Gen 2 are supported via link down training only.

Let me know if further clarification is needed.

Regards,

Wincent_Intel

[emrahener]

Hi Vincent,

I have no further questions.

Kind Regards,

Emrah ENER

[Wincent_Altera]

Hi

Thanks for confirming the answer

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Wincent_Intel