Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18972 Discussions

Linear phase detector implementation for clock and data recovery in FPGA

ArthurDent
New Contributor I
305 Views

Hi

I am working on a clock-data recovery (CDR) design where the input data stream is  60Mbps (8B10B encoded).  Currently I have a working CDR design which uses a binary phase detector (aka. Alexander phase detector) implemented in a Cyclone 10 LP FPGA with an external loop filter and a VCXO.

The binary phase detector (BPD) is straight forward to implement in an FPGA, but the a major drawback is the nonlinearity. This makes it very difficult to calculate the loop bandwidth, and jitter peaking can be a problem in cascaded systems.

I would prefer to use a linear phase detector, but many of these detectors tends to combine clocks an data signals which is not "FPGA standard", and can be dependent on routing delay.

Can anyone recommend (and have experience with) a linear phase detector for CDR which is suitable for FPGA implementation?

BR
AD

 

0 Kudos
1 Solution
ArthurDent
New Contributor I
199 Views

I have decided to drop the FPGA implementation of the CDR, and will look for an external solution.

View solution in original post

2 Replies
SyafieqS
Moderator
231 Views

Hi Vidar,


Any update on this?


ArthurDent
New Contributor I
200 Views

I have decided to drop the FPGA implementation of the CDR, and will look for an external solution.

Reply