For this AXI master coding, how do I guarantee AW* payloads are sent first, followed by W* payloads without violating AXI protocol (a master must not wait for AWREADY to be asserted before driving WVALID) ?
always @(posedge clk) begin if(reset) begin o_axi_wvalid <= 0; end else if(!(o_axi_wvalid && !i_axi_wready)) begin // Note that both o_axi_awsize , o_axi_awlen are of hardware constants, so no multiply hardware // since this is for testing, WDATA just uses some values up to the total size of the write address space // see [url]https://i.imgur.com/LBO9pQz.png[/url] in which AW* payloads are sent first, followed by W* payloads // Note: a master must not wait for AWREADY to be asserted before driving WVALID o_axi_wvalid <= (o_axi_wlast) ? 0 : (o_axi_wdata < (o_axi_awsize*o_axi_awlen)) && o_axi_awvalid; end end
Sorry for the very late response. Here is simply design for AXI master. for write transaction. The idea is to use finite state machine for write address channel(AW) and write data channel(W) for AXI master write transaction. To start the write transaction, the axi master uses the user interface information and send AXI write address and control information on write address channel. You have to keep address and control on bus and assert 'AWVALID' signal until the slave accepts and assert the 'AWREADY' signal. For write data channel, the transfer occur when both 'WVALID' and 'WREADY' signal is high as the master send each item of write data from user interface. For write response channel, The master must assert the WLAST signal while it is driving the final write transfer in the burst. During this burst mode, the next data should be on bus after slave receive previous data by asserting WREADY signal. If you have license for Mentor Graphics AXI Verification IP Suite License (Intel FPGA Edition) you can use as it provides bus functional models for simulation and verification for your AXI design.