Looking for an example Max-10 Quartus project with LVDS I/O

[SBake8]

I'm looking for an example Max-10 Quartus project that uses LVDS I/O. I do not need SERDES. I plan to run the LVDS pins at 100MHz clock rate. I plan to use Verilog source code. Thanks,

[SreekumarR_G_Intel]

Hello there ,

sorry for late response ;

Hope you might already get some example , if not just curious , did you get chance to check in intel fpga cloud.

https://fpgacloud.intel.com/devstore/platform/?acds_version=any&family=max-10

Thank you ,

Regards,

Sree

[JPott5]

There is nothing there for LVDS on the Max 10. Are there any other sources of example code for an LVDS Receiver SERDES on the Max10?