I'm looking for an example Max-10 Quartus project that uses LVDS I/O. I do not need SERDES. I plan to run the LVDS pins at 100MHz clock rate. I plan to use Verilog source code. Thanks,
Hello there ,
sorry for late response ;
Hope you might already get some example , if not just curious , did you get chance to check in intel fpga cloud.
Thank you ,