Loop index overflow problem

[Altera_Forum]

Hi there, 

 I've wrote a little VHDL program in Quartus II. I'd like to separate one big std_logic_vector into small fix-length std_logic_vectors and the compile told me that the index is out of range, very strange...  source code: =================================================== load_p:process(i_clk,i_datain)  variable p_count:integer range 0 to 8*8*i_width; --i_width is a constant variable p:std_logic_vector(i_width-1 downto 0);--buffer of one data  begin  p_count := 8*8*i_width-1; --counter for index  for i in 0 to 63 loop  p := datain(p_count downto p_count-i_width+1); --buffering (line 30) p_count := p_count-i_width; --get next line index  end loop;   end process;  ======================================================= the compiler says:  Error (10528): VHDL error at df_loader_p.vhd(30): value "-1" is outside the target constraint range (0 to 512)  Help me out , thx!!!:(

[Altera_Forum]

--- Quote Start ---  very strange...  --- Quote End ---  The code does exactly what you have written.   In the last iteration, it tries to decrement p_count from 7 to -1, although everything is finished. Instead of decrementing a variable, you may want to calculate the p_count value at the entry of each iteration.

[Altera_Forum]

Another question - is this testbench code?

[Altera_Forum]

--- Quote Start ---  The code does exactly what you have written.   In the last iteration, it tries to decrement p_count from 7 to -1, although everything is finished. Instead of decrementing a variable, you may want to calculate the p_count value at the entry of each iteration.  --- Quote End ---    Hi, thx for reply,  i don't really understand what is your suggestion means...you mean i have to unroll the iteration?  and i think you'er right about the iteration , that after the "last" iteration (i=63), the i continue increasing to 64, like C language or any other program language, but with the entry constrain , the procedure in the iteration shouldn't be executed...  i think i have to loose the constrain of the range of p_count to -1 to 8*8*i_width...

[Altera_Forum]

--- Quote Start ---  Another question - is this testbench code?  --- Quote End ---    no, it's a small single component in a big system

[Altera_Forum]

Or you could start Pcount at its upper bound and just change the datain extraction.

[Altera_Forum]

--- Quote Start ---  no, it's a small single component in a big system  --- Quote End ---    Then your design is very flawed. It is not going to produce synchronous logic because you have not included the clock inside your process.

[Altera_Forum]

--- Quote Start ---  Then your design is very flawed. It is not going to produce synchronous logic because you have not included the clock inside your process.  --- Quote End ---    :D, no ,i use two processes method, this is only the combinational part, i have deleted the sequential part...

[Altera_Forum]

ok, then i 've changed the P_count to increasing order, problem still... 

 p_count := 0; --counter for index  for i in 0 to 63 loop  p := datain(p_count+i_width-1 downto p_count); --buffering  p_count := p_count+i_width; --get next line index    end loop;  and the compiler says:  Error (10528): VHDL error at df_loader_p.vhd(30): value "512" is outside the target constraint range (0 to 511) T.T

[Altera_Forum]

Ok - It was because you had included the clock in the sensitivity list and not used it - it is a common newbie mistake.

[Altera_Forum]

You have changed the constraint range - in the origional code you posted : 

 variable p_count:integer range 0 to 8*8*i_width; --i_width is a constant  Which should give you 0 to 512.

[Altera_Forum]

--- Quote Start ---  Ok - It was because you had included the clock in the sensitivity list and not used it - it is a common newbie mistake.  --- Quote End ---    i think at the synthesis phase, the compile actually add all the signals to the sensitive list.

[Altera_Forum]

No - the synthesisor ignores the sensitivity list. It will warn you if there are signals missing from the list, but it makes no difference to the logic created.

[Altera_Forum]

--- Quote Start ---  You have changed the constraint range - in the origional code you posted :  variable p_count:integer range 0 to 8*8*i_width; --i_width is a constant  Which should give you 0 to 512.  --- Quote End ---    that is because the iteration should stop at 511

[Altera_Forum]

How can it stop at 511 when you add 8 each time?

[Altera_Forum]

--- Quote Start ---  How can it stop at 511 when you add 8 each time?  --- Quote End ---    because i only have 64 iterations, and started from 0, the last data bit range should be 504 to 511. i have ran this similar algorithm in C Code, the iteration stop at 511, no error appeared.

[Altera_Forum]

int i,j; 

j=0;  for(i=0;i<=63;i++){  printf("%d,%d,%d\n",i, j,j+7);  j+=8;  }  the last line of the output is 63,504,511

[Altera_Forum]

thats because j stops at 504, and you print j+7 

I dont see a p_count + 7 offset anywhere in your VHDL.  You'll find that j actually finishes the loop on 512.

[Altera_Forum]

--- Quote Start ---  thats because j stops at 504, and you print j+7 I dont see a p_count + 7 offset anywhere in your VHDL.  You'll find that j actually finishes the loop on 512.  --- Quote End ---    i wrote this,  p := datain(p_count+i_width-1 downto p_count); --i_width=8, so this is my "p_count+7" p_count:=p_count+i_width;

[Altera_Forum]

yes, and just like in the C, you have the extra p_count := p_count+i_width which pushes p_count to 512 as the loop exits. 

 you have exactly the same thing with j. It ends the loop on 512.

[Altera_Forum]

--- Quote Start ---  yes, and just like in the C, you have the extra p_count := p_count+i_width which pushes p_count to 512 as the loop exits.  you have exactly the same thing with j. It ends the loop on 512.  --- Quote End ---    ok, i understand, the iteration actually enter the overflow situation and then exit