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I would like to use the LVDS SERDES tx/rx modules for chip to chip communication. I'm trying to figure the easiest way to configure the modules.
1) Is it possible to setup the lvds_tx and lvds_rx to use external tx and rx clock while still sharing the same fpga fabric clock (parallel clock)? 2) Do I need to use DPA if I use external clocks for tx and rx serial paths? 3) Any recommendations on a better way of implementing this interface? thank you.Link Copied
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