M9K Block RAM Endianess When Configured For Mixed Width Data Ports

[Dagobah]

When using an M9K Block RAM in simple or true dual port mode with mixed width data on a MAX10 FPGA, where can I find documentation on the Endianess of a Write on one Port and a Read on the other port?

For example:

        Port A: 16 Bits Wide Data

        Port B: 8 Bits Wide Data

        Write Port A with data 0x1234 at address 0x00.

        Read Port B at address 0x00 returns 0x12 or 0x34?

No hard or soft processors are involved and the FPGA fabric alone is doing the reading and writing on the two ports.  I've read through many documents on the M9K Block RAM and have not found this particular timing diagram or explanation.  I could resort to simulation to find out the answer but would prefer a documented answer in the FPGA literature.  A similar question could be posed for the M20K Block RAM on more advanced FPGA's.

[Dagobah · Accepted solution]

With simulation of M9K Block RAM in simple or true dual port mode with mixed width data on a MAX10 FPGA, I have verified that the natural storage of the RAM is Little Endian.   In the example above, a write to Port A at sixteen bits with data 0x1234 at address 0x0 results in a read on Port B at eight bits with data 0x34 at address 0x0.  This is consistent with a RAM initialization file of 8 bit data words equal to the address such that the data sequence 0x00, 0x01, 0x02, 0x03, 0x04, ... reads back on both ports as data 0x0100 for sixteen bits on Port A at address 0x0 and data 0x00 for eight bits on Port B at address 0x0.  This also make sense from the RAM storage view as a linear array.  Additional circuitry would be required to convert the RAM storage array to Big Endian format between mix width ports.  The Byte Enable signals, when used in that mode, also agree with the little end bytes at lower addresses.