Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18983 Discussions

MAX 10 ADC Simulation

Honored Contributor II



I'm using the MAX 10 Development Board and want to simulate the ADC (Modular Dual ADC IP core). 


According to the manual the ADC samples are stored in the sample storage core and after receiving a block of ADC samples it asserts an Interrupt Signal. The samples can retrieved through the Avalon-MM slave interface. 

What i want to do is, to post-process the received ADC values. Therefore i will wait for the Interrupt and then read the values out of the ADC Sample Register. 


So far, i created a Modular Dual ADC IP core and its simulation model out of the Platform Designer (Qsys) see attachment. 

I created a simple testbench where i just have a clock generator. 


The simulation failed with many errors like:  

"Instantiation of 'ADC_ADC_control_internal' failed. The design unit was not found.." and similar errors. 

"Port "configupdate" of entity "adc_pll" is not in the component being instantiated." 

I don't know why it is missing because i generated it from Qsys and didn't write the codes by my own. 


Can someone help/give me an advise how to approach this task? 


Best regards!
0 Kudos
1 Reply
Honored Contributor II



Check the Link. 


Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)