MAX 10 CPLD VCCIO design consieration

[yzhu12]

Hello, there

 We have read that

For the V36 package of the 10M02 device, the VCCIO of these groups of I/O banks
must be the same:
— Group 1—banks 1, 2 and 8
— Group 2—banks 3, 5, and 6

We are not sure what V36 package refers to. The device number that we are interested in is 10M02SCU168I7G, shall we condsider that the above condition is necessary for it?

If so, what shall we expect if we violate this guideline.

Hope someone can confirm it for us. Would relly appreciate the help.

Regards,

Yuanchen Zhu

[AqidAyman_Intel]

Hi Yuanchen Zhu,

Thank you for reaching out Intel FPGA Community.

Based on Intel® MAX® 10 FPGA Device Overview, V36 package refers to Wafer-Level Chip Scale (WLCSP) package with 36 pins.

I believe the part number that you interested in is not included in the mentioned condition because it is not the V36 package.

For more information on the MAX 10 Device ordering information, refer to this link: https://www.intel.com/content/www/us/en/docs/programmable/683658/current/device-ordering-information.html

I hope this information helps you moving forward.

Regards,

Aqid

[AqidAyman_Intel]

Hi Yuanchen Zhu,

I wish to follow up with you.

Did you need any more support on this? Or any clarification needed?

Regards,

Aqid

[yzhu12]

Sorry for not being able to reply in the last few days,  was having trouble making a reply on the website due to technical problem.

One last question, is there any reference layout design file provided for MAX 10 to check out? Thanks.

Regards,

Yuan

[AqidAyman_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.