Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19345 Discussions

MAX-10 FPGA, Voltage level on PLL_CLKOUT pins

Altera_Forum
Honored Contributor II
822 Views

Hi all, 

 

I want to use one of the PLL_CLKOUT pins on the 10M50DAF256 FPGA to output a clock signal to an external ADC component that requires 1.8V voltage level. 

If for example I will use the pin "IO_6_D14/PLL_R_CLKOUTP/DIFFIO_RX_R69P" as a PLL output (PLL_R_CLKOUTP), will the voltage level of my clock be the same as for I/O bank 6, or will it be 1.2V as the VCCD_PLL supply voltage? 

 

Best regards, 

Vadim.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
120 Views

Hi,  

 

Voltage level will be same as bank voltage where pin is located.
Altera_Forum
Honored Contributor II
120 Views

Thanks for the quick reply!

Reply