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Hi all,
I want to use one of the PLL_CLKOUT pins on the 10M50DAF256 FPGA to output a clock signal to an external ADC component that requires 1.8V voltage level. If for example I will use the pin "IO_6_D14/PLL_R_CLKOUTP/DIFFIO_RX_R69P" as a PLL output (PLL_R_CLKOUTP), will the voltage level of my clock be the same as for I/O bank 6, or will it be 1.2V as the VCCD_PLL supply voltage? Best regards, Vadim.- Tags:
- pll
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Hi,
Voltage level will be same as bank voltage where pin is located.- Mark as New
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Thanks for the quick reply!

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