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Altera_Forum
Honored Contributor I
2,629 Views

MAX 10 Flash programming

Hi, 

 

In MAX 10 FPGA, when the CFM will program ? What are the signals are related to flash ? CONFIG_SEL pin is used to select the CFM0 and CFM1 but, how the process will work ? Please explain if anyone knows. 

 

Thanks in advance. 

 

Regards, 

KVL
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11 Replies
Altera_Forum
Honored Contributor I
297 Views

I think you need to explain exactly what you're trying to do. Referring to your last post and this one, I'm not sure you understand the purpose of the CFM. It's used to store your MAX 10 FPGA's design. 

 

From the document I pointed you at last time: 

--- Quote Start ---  

You need to program the configuration data into the configuration flash memory (CFM) before internal configuration can take place. The configuration data to be written to CFM will be part of the programmer object file (.pof). Using JTAG In-System Programming (ISP), you can program the .pof into the internal flash. 

--- Quote End ---  

 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
297 Views

Actually, I'm planning to use USB (via FTDI) to program the internal flash. I am confusing with how data and control signals are connected in between FTDI and FPGA to program the CFM.

Altera_Forum
Honored Contributor I
297 Views

Without specific logic implemented in the MAX10, JTAG is the only interface available for flash programming. Quartus only supports flash programming through Altera programming adapter, but it's possible to use generic JTAG programming files with third party tools. Some may be able to implement a JTAG programmer through FTDI USB adapter. 

 

The other option is use a dual flash configuration and program the application part of the flash in remote system upgrade mode. The data can be streamed to the MAX10 device via any interface of your choice, e.g. UART. 

 

Both options are discussed in detail in the MAX10 handbook chapter "MAX 10 FPGA Configuration Design Guidelines".
Altera_Forum
Honored Contributor I
297 Views

You program the CFM via JTAG. You can't program the internal FLASH directly from other pins. So, an FDTI device won't help you. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
297 Views

Thank you FvM and Alex. 

Now, I understood and I have another doubt regarding USB Blaster. In USB Blaster circuitry, CPLD is necessary to use ?
Altera_Forum
Honored Contributor I
297 Views

The header is placed between FTDI and CPLD (USB Blaster circuit). What is the purpose of that header ? please clarify.

Altera_Forum
Honored Contributor I
297 Views

Yes. The CPLD is essential. The unpopulated header is for programming it. What's programmed into it is a closely guarded Altera secret. Don't expect to be able to replicate it. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
297 Views

Okay. Thank you Alex.

Altera_Forum
Honored Contributor I
297 Views

May I know what is the purpose of CPLD ? It would be great if anyone clarifies my doubt. 

 

Regards, 

Lakshmi
Altera_Forum
Honored Contributor I
297 Views

It generates the programming signals (JTAG or PS) based on the data from the FTDI device. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
297 Views

A little bit of overview info here, in chapter 2: https://www.altera.com/literature/ug/ug_usb_blstr.pdf 

 

There is very little public documentation around on what goes in the CPLD as far as features/functionality. However, the Altera JAM STAPL (https://www.altera.com/support/support-resources/download/programming/jam.html) player does/did support using the USB Byte Blaster in simple JTAG bit banging mode. From the header comments in the jamstub.c routine: 

 

/* The following code doesn't fully utilize the possibilities of the * USB-Blaster. It only buffers data up to a maximum packet size of 2 bytes. * The normal maximum packet size is up to 64 bytes (but would require a * major change to the logic of this program). * * Actually, the USB-Blaster offers a byte-shift mode to transmit up to 504 data * bits (bidirectional) in a single USB packet. A header byte has to be sent as * the first byte in a packet with the following meaning: * * Bit 7 (0x80): Must be set to indicate byte-shift mode. * Bit 6 (0x40): If set, the USB-Blaster will also read data, not just write. * Bit 5..0: Define the number N of following bytes * * All N following bytes will then be clocked out serially on TDI. If Bit 6 was * set, it will afterwards return N bytes with TDO data read while clocking out * the TDI data. LSB of the first byte after the header byte will appear first on TDI. */ /* Simple bit banging mode: * * Bit 7 (0x80): Must be zero (see byte-shift mode above) * Bit 6 (0x40): If set, you will receive a byte indicating the state of TDO in return. * Bit 5 (0x20): Output Enable/LED. * Bit 4 (0x10): TDI Output. * Bit 3 (0x08): nCS Output (not used in JTAG mode). * Bit 2 (0x04): nCE Output (not used in JTAG mode). * Bit 1 (0x02): TMS Output. * Bit 0 (0x01): TCK Output. * * For transmitting a single data bit, you need to write two bytes. Up to 64 * bytes can be combined in a single USB packet. * It isn't possible to read a data without transmitting data. */  

 

I have used this code as part of a custom JTAG scanner that employed the Altera USB Blaster as the hardware interface.
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