I had raised this issue before. The question was unfortunately closed off without a solution.
We are using JAM player from an embedded MCU.
To load program from quartus, we use the .pof file with the programmer and USB blaster II
The program is ported to the embedded target and we have four pins connected to the MAX10 to program the FPGA.
I tried two options:
1. Disabled the ISP and generated the JAM file and converted it to a hex file and used it to program the FPGA.
I get the exit code 10 as mentioned before. The image in fpga is unaffected.
2. Enabled the ISP and used the generated the JAM file to program the FPGA. I got exit code 0!! from both Program and Verify action.
After power cycling though, I saw the FPGA logic is absent and it is at the reset state.
So did the above option just erase the flash? In that case, why would I get successful programming confirmation from JAM player?
Or do I need to try something else to transfer the logic to SRAM if I use the ISP option?
Your setup is very similar to ours only we use a 10M04SCU169A7G.
Two differences I noticed:
1. In Programmer when we convert pof to jam, we don't check any Program/Configure or Verify checkboxes. We do check the Enable real-time ISP checkbox.
2. What is jbc.exe? I cannot find it in my installation of Quartus. We use quartus_jbcc -n xxx.jam xxx.jbc to convert jam to jbc.
Then we convert the jbc to a byte array and embed it into our MCU firmware. When calling jbi_execute in the MCU we use action PROGRAM together with optional procedure DO_VERIFY=1.
Not sure if it helps you but this works for us.
Thanks a lot for the suggestions.
I created a jam file with Program/Configure or Verify checkboxes unchecked with and without the real-time ISP enabled.
I also used the quartus_jbcc.exe to generate the jbc file.
We call the jbi_execute twice. Once with action "PROGRAM" and secondly with "VERIFY". Ill check how to enable the optional procedure.
As for the results, it is unfortunately still the same. When I disable ISP, I see that the generated filesizes are higher but I get the exit_code 10 "exit_string = "Device programming failure";
If I enable ISP, the device is erased but not programmed.
Thank you very much for sharing your experience here. It was really helpful to us. We got success to program internal flash of Max 10 FPGA by using steps mentioned here.
We also took some reference from AN904 (1. Intel® MAX® 10 Hitless Update Implementation Guidelines ).
Our target device was 10M08SCU169C8G.
We followed the steps mentioned below:
- Created IPS file as mentioned in section 1.5.1 in AN904.
- Used POF file. (This POF was generated along with SOF file when Quartus design was compiled.)
- We didn't make any change in pin state in ISP Clamp State Editor.
- Generated .JBC file as mentioned in section 1.6.1 in AN904.
- While doing this, we selected option to Enable real-time ISP to allow background programming when available
- Also selected ISP Clamp option.
- While calling jbi_execute function, we selected PROGRAM action.
- Once programming was done, we applied power cycle. And in next cycle, we noticed that FPGA was configured from internal flash!
Note: .jbc file created without 'Enable real-time ISP to allow background programming when available' didn't work and its file size was also more compared to jbc file created with this option on. Jay also mentioned about file size in this his post.
Have a Great Day!