MAX 10 JTAG overshoot

[Ron_at_Compunetix]

Concerning MAX 10 JTAG pins, I have read everything I can find on these pins and am getting mixed messages about what I can and cannot do. I need to run these pins at 3.3V since I need the other IOs in the block. I run the JTAG interface at 2.5V but since I have several devices in the chain, I buffer TMS and TCK and send to the devices at 3.3V. I am seeing some overshoot at the MAX 10 but how much is too much? Since the JTAG pins do not have PCI clamping diodes, how much overshoot can they withstand? Do they conform to the overshoot life expectancy tables for 3.3V? I am running the interface and have not experienced any issues but sample size is small. And since the FPGA is programmed and boundary scanned typically once during manufacture, should I be concerned, even if I damage a JTAG pin? Perhaps I'm being overly paranoid. What's your opinion?

[NurAiman_M_Intel · Accepted solution]

Hi,

Thank you for contacting Intel community.

If you have followed Intel Max 10 design guidelines and Intel Max 10 configuration userguide, overshoot should be prevented. Unless if you have a lot of board design or the board design is not correct then overshoot might occur, but it is a very rare case.

In Intel Max 10 configuration userguide mentioned, to prevent voltage overshoot, you must use external diodes and capacitors if maximum AC voltage for both VCCIO and JTAG header exceed 3.9 V. However, Intel recommends that you use the external diodes and capacitors if the supplies exceed 2.5 V.

Max 10 Design guidlines:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_guidelines.pdf

Max 10 configuration userguide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

Thanks.

Regards,

Aiman

[Ron_at_Compunetix]

Many thanks! Ron.

You can close this issue.