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MAX 10 On-Chip Flash IP core read incorrect data

YDeal
Beginner
137 Views

I use the Quartus Prime Standard 17.0.2  (Certified Version) and I observe random failure on read access on On chip Flash IP.

The design is implemented on 3 différents MAX10 FPGA and only one have the probleme.

 

I check, all constraints and timings report.

The probleme is random and routing dependant.

 

I found with google this article : Why does MAX 10 On-Chip Flash IP core read incorrect data at odd... (intel.com) and I need more information about this bug.

 

I can't change the tool version as is the last certified version.

 

Observed bug

Data read Ok 

01000202 00011700 20202020 20202020 20202020 20202020 20202020 202020E0 02080500 30303030 31F10002 58022020 20202020 20202020 20202020 20202020 20464449 4F445452 32303030 30323132 32382041 20202020 58202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020

Data read NOK: 

    010002 63010002 63010002 63010002 20202020 20202020 20202020 20202020 E0020805 E0020805 E0020805 E0020805 20202020 20202020 20202020 20202020 20204644 20204644 20204644 20204644 32323820 32323820 32323820 32323820 20202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020

The data seems shift and repeats 4 times.

 

Component : MAX 10 10M16DAF256I7G

Tool : Quartus Prime Standard 17.0.2  (Certified Version)

0 Kudos
2 Replies
SyafieqS
Moderator
105 Views

Hi Deal,


Are all three device have different bitstreams? If yes,

What I ccan think of is, assuming timing is clean, can you try to use other bitstream and program the device and see if flash read still behaves incorrectly.


How did you read the data from? Using nios? 



SyafieqS
Moderator
73 Views

Deal,


May I know if there is any update?


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