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Altera_Forum
Honored Contributor I
1,259 Views

MAX 10 True LVDS Tx where are you??

I'm having some issues trying to id the True LVDS Tx pins on the MAX10, 10M04SCU169. I have looked at the datasheet "MAX 10 High-Speed LVDS I/O User Guide" and it says that the bottom bank 3 has true LVDS Tx buffers (page 2-13)... However it looks like only 9 out of 14 diff. pairs in bank 3 support have true LVDS Tx buffers (page 2-3). The problem now it which 9 pairs have these true LVDS Tx buffers??? I couldn't find anything that explicitly says "hey these are the pins you are looking for". I think I might have found a way to id them in Quartus Prime by looking in Pin Planner and the Pin Properties window under Special function and finding the label DIFFIO_TX_RX_xx, but that is just a guess. 

 

Does anyone know if there is a document that explicitly calls out which pin pairs on the MAX10 support True LVDS Tx? Thanks!
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Altera_Forum
Honored Contributor I
40 Views

I'm sure the pin files would have it, but still hunting for them in a spreadsheet. Make a design with 9 outputs, make an IO assignment of LVDS and location of bank 3. Quartus will place them in the legal locations.

Altera_Forum
Honored Contributor I
40 Views

The answer is clearly given in the 10M04SC pinout file, which shows DIFF_IO_TX_RX pairs B1, B3, B5, B7, B9, B10, B12, B14 and B16 as dedicated LVDS outputs. I'm quite sure, the difference between dedicated and emulated outputs is also visible in the Pin Planner.

Altera_Forum
Honored Contributor I
40 Views

It is in fact by indicating either DIFFIO_IO_TX_RX (true LVDS) or DIFFIO_IO_RX (emulated) in the pin legend.

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