EDIT: It looks like I was making some mistakes elsewhere, the below works correctly for anyone else looking to erase the UFM using low level HDL code.
Hello! I am working with the 10M16SCU169I7G and can successfully read from the UFM (after applying the patch from the knowledge base), but I am having trouble implementing the erase and write operations. Would you have any advice on where my process is going wrong, or any example code or projects I could look at?
I am trying to erase the UFM contents a sector at a time using a simple FSM module. It is currently doing this:
Waiting for the memory to be idle by polling the CSR register:
clock 0: csr_addr = 0, csr_read = 1,
clock 1: csr_addr = 0, csr_read = 0, check lowest two bits of csr_readdata here
When those two bits are 2'b00, then write to the write protection bits:
csr_addr = 1, csr_write = 1, csr_writedata = 32'h7c7fffff (I'm actually using {4'b1111, 5'b11000, {(23){1'b1}}}) here
Then write the sector number to start the erase:
csr_addr = 1, csr_write = 1, csr_writedata = {4'b1111, 5'b11000, cur_sector + 3'b001, {(20){1'b1}}}, cur_sector = 0
And then polling the CSR status register like above to wait until it's no longer busy, and then it increments cur_sector to repeat the process for cur_sector from 0 to 2 (corresponding to sectors 1, 2, and 3), and all transitions are happening the positive edge of the same clock that is being fed into the on chip flash. I have tried swapping the order of the CSR busy polling with the write protection but neither order seems to make a difference, the Flash retains its original contents
