MAX 10 programming flow via JTAG

[LZANU]

Hi All!

I have the following questions about the correct sequence to follow for MAX 10 programming devices via JTAG, especially the 10M04SAU169.

1. I noted that once converted a pof file to SVF and compared it to a BSDL 1532 file (e.g. 10M04SAU169_1532.bsd), it adds also the following steps:

-------------------------------------------------------------------------------

!
!Max 10 IDCODE
!

...

SDR 23 TDI (500008);
SIR 10 TDI (205);
RUNTEST 128 TCK;
SDR 32 TDI (00000000) TDO (1E000000) MASK (FF800000);

-------------------------------------------------------------------------------

For a 10M02SC,  the mask is different instead:

-------------------------------------------------------------------------------

!
!Max 10 IDCODE
!

...

SDR 23 TDI (500008);
SIR 10 TDI (205);
RUNTEST 128 TCK;
SDR 32 TDI (00000000) TDO (1E000000) MASK (9F800000);

-------------------------------------------------------------------------------

I cannot find anything in the BSDL 1532 programming flow about it. Is it a mandatory step? May I know which is its purpose?

2. The SVF file automatically skips the blank locations (if present) in order to shorten the programming time.  I noted that it does not follow the BSDL 1532 flow, but it translates the address every time is needed. For example:

  -------------------------------------------------------------------------------

!
!Max 10 Program CFM1
!

SIR 10 TDI (203);
RUNTEST 128 TCK;
SDR 23 TDI (001700);
SIR 10 TDI (2F4);
RUNTEST 128 TCK;

...

SIR 10 TDI (203);
RUNTEST 128 TCK;
SDR 23 TDI (021700);
SIR 10 TDI (2F4);
RUNTEST 128 TCK;

...

-------------------------------------------------------------------------------

The BSDL 1532 flow provides only the first address instead:

-------------------------------------------------------------------------------

"FLOW_PROGRAM2 (array_cfm_2) " &
"INITIALIZE" &
"(ISC_ADDRESS_SHIFT 23:002200 WAIT TCK 1)" &
"REPEAT 20992 " &
"(ISC_PROGRAM 32:? WAIT 305.0e-6)," &

-------------------------------------------------------------------------------

I cannot find anything about how to translate an address to the corresponding "JTAG" value to be shifted out. Is there any document that expains how to do that (we already have the CNDA number if needed)?

Thanks in advance for your help!

Best Regards,

Luca

[NurAiman_M_Intel]

Hi,

Do you get any error when programming MAX10? Have you follow the MAX10 configuration userguide?

https://www.intel.com/content/www/us/en/docs/programmable/683865/current/fpga-configuration-overview.html

Regards,

Aiman

[LZANU]

Hi Aiman,

Thank you for your reply.

Do you get any error when programming MAX10?

It is working fine. We have compared the content with Quartus Programmer and no difference is found. However, I'm not sure if the sequence added by the SVF file (see step 1) is mandatory or not. 

Have you follow the MAX10 configuration userguide?

I cannot find anything in the MAX10 configuration user guide or in other documents. We followed the BSDL 1532 and another document your colleague sent us "MAX10_programming_spec_Ver6.pdf - 16S-29647 04" (by the way, is there a new version available?). We are only interested in the JTAG programming flow as a third party programmer.

We do not support SVF or JAM formats, but only POF format.  The programming algorithm must then be developed by us and we are focusing on all the steps added in the SVF file. Is there a document that expains how to convert a POF into a SVF file for MAX 10 devices? Is it described in a file in the qprogrammer directory in a human readable format?

Best Regards,

Luca

[NurAiman_M_Intel]

Hi,

Per my understanding, you are not using Quartus to program.

You can refer the KDB below on steps to generate .svf file. Do you follow the steps?

https://www.intel.com/content/www/us/en/support/programmable/articles/000085709.html

Regards,

AIman

[LZANU]

Hi Aiman,

You are correct. The goal is to program the MAX 10 devices  with our third party programmer. In addition, we do want to manage the pof file directly, without converting it to SVF or JAM with Quartus.

We are already able to manage the pof file. For the programming algorithm we are following the BSDL 1532 & MAX10_programming_spec_Ver6.pdf  documents. However, my first question is why the SVF file generated with Quartus includes also the following JTAG sequence: 

SDR 23 TDI (500008);
SIR 10 TDI (205);
RUNTEST 128 TCK;
SDR 32 TDI (00000000) TDO (1E000000) MASK (FF800000);

I cannot find anything about it. I'm worried that it must be performed even if not described in any document.

Regarding my second question, we have already find out the solution: the ISC address is simply the address with MSB first. 

Best Regards,

Luca

[LZANU]

Hi Aiman,

The reason I am also asking for this is because of an issue while re-programming the MAX 10 if the CFM is secured (all the content is read out as 0x0000..). In this scenario,  the BSDL1532 sequence fails: the CFM memory is still read out with 0x00 even after a DSM Clear command.  Of course, Quartus can reprogram it successfully instead. I'm worried then that the BSDL 1532 file does not take into account all possible scenarios.

As I can see from the Handbook on page 294, I suspect that the CFM Verify Protect may be enabled. In that case, what can I do to unlock it? I would expect that after a DSM Clear the Verify Protect feature is turned off.

Best Regards,

Luca

[NurAiman_M_Intel]

Hi,

Apologize for the delay in response as I was on emergency leave.

This is to let you know that I have consult our engineering team for this case. I shall let you know once they have provide their feedback.

Thanks.

Regards,

Aiman

[LZANU]

Hi Aiman,

Thank you for your help.

I discovered that I can remove the Verify Protect feature by performing the DSM Clear command and disconnecting to the target.  I noted this is the only way to read out again the content of the CFM memory (instead of 0x00). Not sure if it is the recommended way to do that.

Best Regards,

Luca

[NurAiman_M_Intel]

Hi,

What Quartus version was used to generate the SVF?

Regards,

AIman

[LZANU]

Hi Aiman,

It is Quartus Prime 20.1.

Best Regards,

Luca

[NurAiman_M_Intel]

Hi,

To confirm, now you are able to remove the verify command, you do not get any error? The design now works fine? The BSDL1532 sequence no longer failed?

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you