MAX 5 Power Rail Ramp Times

[Ian_Maw_Chelton]

Hi all,

I can't see a minimum or maximum ramp time in the MAX V data.

Is there a specification for this, or is any ramp time / rate acceptable ?

Are the power supply ramps required to be monotonic ?

Thanks.

[AqidAyman_Intel]

Hello,

Thank you for reaching out Intel FPGA Community.

I checked the documentation, and as you mentioned there is no mention on the ramp up time for the device. What I understand is that this device does not have the requirement to power up sequence. It means that you just need to follow the restrictions of getting into user mode as defined in the documentation. Refer on Chapter 4, page 4-5 in the below link:

https://www.intel.com/content/www/us/en/content-details/654928/max-v-device-handbook.html?wapkw=max%20v%20&DocID=654928

As for the power supply, it is always recommended to be monotonic. I found information from the internal resources as below:

"We recommend in this case to have a monotonic rise because you don't want the power to dip below the download SRAM entry point which is 1.55V after passing it. If it falls below 1.4V as it enters user mode, functionality of the device is not guaranteed."

I hope the information shared helps you moving forward.

Regards,

Aqid

[Ian_Maw_Chelton]

Thanks Aqid.

[AqidAyman_Intel]

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