I would like to have some information about MAX II (PN: EPM2210F256I5N) decoupling capacitor. Reading Design Guidelines CPLD needs 0.1 mF for each supply pin, in my opinion it's a lot far away common decoupling capacitor, moreover MAX II EVAL uses 0.1 uF capacitor (and for less than 1 for each pin). In the end is correct what is written in Design Guideline or there is some mistake?
Obviously this question arises from the fact that it is not possible to install so much capacity per pin and I would like to install about 10 uF of cumulated capacity on the CORE of the CPLD itself, do you think it is enough?
Thanks a lot
The design rule I basically use is the largest available capacitance in the least inductive package per pin.
So for most TQFP devices I use an 0603 size device typically about 1uF per pin using a low inductance PCB footprint.
This means VIA in PAD, if possible, or else two VIAs per pad with PCB surface stubs that are as short as possible.
For BGA devices I like to go with VIA in PAD and bridge an 0402 device across a power/ground pin pair under the device.
Usually on the 45deg diagonal works best for fine pitch BGA device footprints.
Larger bulk capacitors in the 10uF-47uF range can surround the device, but they are nowhere near as critical.
Anybody that says spray a range of small devices in the 100pF to 10nF range are spouting nonsense IMHO.
Done this for 25+ years of high end design using ASICs, FPGAs, CPUs and other state of the art devices.
Never served me wrong.
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.