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Honored Contributor I
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MAX II counter output problems

Hello,  

 

I have a problem with 12bit counter with asynchronous clear in MAXII.  

I send 12 bit data in MAX and send them out to two 12bit buses - data for SRAM memory. I use counter for generating addresses for memory and I send them again to two 12bit buses. Together I use 72 pins from total 80 pins - 24 address bits, 12 input data bits, 24 output data bits and rest are some control bits (clocks, enables etc.) The problem is that when I start to send data inside MAX, when I connect more then about 5 data pins, higher adress bits don't get on the bus (lower bits are going without problems). I found out, that it is somehow influenced by input reset pin, which I normally hold inactive (log. 0). If I ground reset of counter in quartus scheme, problem disappears all adress bits get on both busses. 

 

I don't know how to explain this. Is it possiblle that, usage of higher count of pins which have to feed 4x16 bit busses can cause some inductions inside the chip and can cause signal disturbances in parts of design which are according to scheme separated? Has anybody simillar experience? 

 

Clock I send to counter has frequency of about 250 kHz. 

 

 

Thanks  

 

Ales S.
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