MAX V Exposed pad solder reflow problem

[Nakaj]

A reflow soldering failure occurred on the exposed pad on the bottom of the QFP64
pin device of the MAX V device. Please let me know if there is a recommended 
pattern layout for Exposed Pad.
Please let me know if there is a recommended value for the number and diameter of 
through holes to connect the exposed pad to the GND pattern.

[FvM]

Hi,
what kind of failure do you observe, missing connection or short to other pins?

I see a previous discussion related to 64-pin EQFP package https://community.intel.com/t5/Programmable-Devices/Max-V-Stencil-Design-64-Pin-Plastic-Enhanced-Quad-Flat-EQFP/m-p/1574520#M94757

I think, a comfortable option is to place vias beneath the exposed pad, this way you don't need to care for solder drain through vias. As mentioned in my previous post, EQFP package has the problem of clearance tolerance between pad and PCB, about 0.05 to 0.15 mm. You need to supply suffient solder paste to safely bridge the gap.

Regards
Frank