Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19100 Discussions

MAX V: is it okay to leave VCCIO unconnected for unused I/O banks?

fzliu
Beginner
472 Views

We're using the MAX V CPLD for our project (specifically, the 5M80ZM68). This CPLD has 2 I/O banks; one of them is unused in our application. From both a power and performance perspective, is it okay to leave VCCIO unconnected for that bank? Thanks!

0 Kudos
1 Reply
YuanLi_S_Intel
Employee
93 Views
Hi Frank, It would be better if you have all the VCCIO connected to power rail. The reason is because MAX has power-on circuitry which will monitor the level of VCCIO during power up. Thus, it is important to have it connected so that the device can be power on successfully. Regards, YL
Reply