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Altera_Forum
Honored Contributor I
1,240 Views

MAX V "Jtag chain problem detected"

Hello 

 

I build a testing device - another one (first works fine). One of the testing steps is programming CPLD Max V 5m80z. All signals have been connected but I have a problem. I tested connections hundred of times and everything is fine but CPLD is not programming. I ran Quartus II Jtag chain debugger and it shows some errors. Even worst it shows four devices in chain which is not true. In addition, the same configuration in first testing device works. In attachment you can find screen from Quartus II. If someone want to see what happens in lines I can upload screens from logic analyser. Is there anyone who knows what's going on :confused:
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5 Replies
Altera_Forum
Honored Contributor I
289 Views

Did you find out what is causing this? I've been having similar JTAG related issues except I have 2 devices in my chain: Stratix IV GX and Max V. In the JTAG Chain Debugger, both devices show up normally most of the time, but, I get the message "Warning: Uncertain JTAG chain". Occasionally it will show an extra device in the chain as you describe. I don't see this on another module that is identical. 

 

Since it was showing an extra device, I had assumed this was something on the clock line with extra clocks being detected somewhere so I started poking around. When I attached the scope probe (3.9pF / 10Mohm) on TCK it works consistently with no errors. The TCK signal looks very clean throughout the chain. All of the other JTAG signals are very clean as well. Anyone have any ideas? Are there any known issues with JTAG on either of these parts (MaxV/StratixIV)?
Altera_Forum
Honored Contributor I
289 Views

Yes, I found the issue. The ground signal in my PCB is not got. I mean the routing is bad, not the connection. There is quite big current flowing through ground line which goes to JTAG connector from others parts on PCB. I cut this path and connected programmer directly by bypass (simple wire). It works perfectly. :)

Altera_Forum
Honored Contributor I
289 Views

Thanks for the update. Glad to hear you got it working.  

 

Mine is working reliably now as well. I added a 1nF capacitor between TCK and GND to slow down the edges. Even though it works, the signal looks like crap compared to what it was before. The clock now looks like a shark tooth rather than a perfect square wave. 1nF is probably too much and I'll probably try 10pF or 100pF. 

 

With that said, I suspect it is the StratixIV causing my problems. Even when extra devices are shown the MaxV (last device in chain) almost always appears correct. The JTAG seems extremely sensitive to the TCK signal. As I said before, the signal integrity was almost perfect when looked at with the scope (only 3.9pF load). Further, I have a few identical modules and I don't see this issue on all of them. I'd be curious to know if anyone else has seen similar issues. The datasheet lists 180mV hysteresis for the TCK pin and I honestly can't see the ripple coming anywhere close to that at any point from what I see on the scope, however, it also works with the scope attached.
Altera_Forum
Honored Contributor I
289 Views

This has been solved for a while now, but, I thought I'd post an update on this issue in case it would help anyone out.  

 

Upon further investigation, the issue was related to an impedance mismatch on the JTAG lines, TCK specifically. The USB blaster is designed with very fast rise times using low impedance 25ohm transmission lines. My board was designed with a 50ohm controlled impedance which caused a mismatch and related reflections at the JTAG connector. The positioning of the Stratix device and routing of the TCK line were such that the reflections caused a slight flattening of the TCK line right at the threshold which was causing "false" clock edges to be detected by the Stratix.  

 

On the scope, the signals looked quite clean and only a very slight flattening could be observed (no ringing), however, it also worked reliably with the scope probe (10Mohm / 3.9pF) attached. I suspect, without the probe the flattening/ripple may have been more pronounced and enough to overcome the specified hysteresis. Also, had the TCK trace length been slightly longer or shorter the flattening would have been moved away from the threshold crossing and there would have been no issue. In the end, a 56pF capacitor was added to the TCK line which slowed the edge down enough so it wasn't an issue.
CDai0
Beginner
289 Views

Hi, where did you find that the USB blaster has line impedance of 25 Ohms, I don't see line impedance in the Intel FPGA USB Download Cable User Guide.

I am also having a JTAG detection issue on some of my boards, and I see that my TCK signal has a voltage drop from VDD which would be consistent with mismatch between 50Ohm on PCB and 25 Ohm line in blaster. However, I don't see any voltage drop on the other JTAG signals and all my lines are the same impedance. Where did you see that the line impedance is 25 Ohms?

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