I have a custom board with a 10M04SAE144. It has a switching power supply, TI's TPS54229 converting +5V to +3.3V for the FPGA. With the external oscillator disabled and a dummy *.pof file loaded into the internal Flash, the chip is consuming around 200mW. The dummy *.pof file has few I/O's declared and all set to floats. There is nothing else in the source file, no combitorial logic or memory declared. Does the 10M04SAE144 really consume this much current in idle? I cannot find a spec for this chip for quiescent current.
I'm presuming you looked at this:https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf You say there are I/O's set to float. Are you referring to the unused pin setting in the Device settings (Device and Pin Options)?
You can run the Power Play tool in Quartus to get an estimation of static and dynamic power dissipation. According to the tool, there will be a relevant static core power dissipation, about 120 mW for a similar 10M04SA configuration. The observed extra might be caused by floating inputs.Means MAX10 single supply devices are not well suited for low power applications.
Yes, I did read the data sheet. But, there is no mention of static power usage. Not that I could find.I declare six I/O's as outputs in the source code. Then assign them to "z". Verilog code: module EPT_4CE6_AF_D1_Top ( output wire [2:0] XIO_1, output wire [2:0] XIO_2, ); assign XIO_1 = 3'hz; assign XIO_2 = 3'hz; ); endmodule The rest of the I/O's are unused in pin setting in the Device settings.
Ok, this sounds like the solution to my problem. There is some mention of how to shut down the core of the device and enter a sleep mode in this design note https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_pwr.pdf (https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_pwr.pdf). However, this power management function does not appear to be a MegaFunction that I can select from Quartus. It looks like custom source code from Altera. So, I will have to download it and see if I can compile it.Also, is there a quick start guide to using the Power Estimator. Altera's user guides are long and boring and I fall asleep half way through executing them. Thanks, Richard
--- Quote Start --- Ok, this sounds like the solution to my problem. There is some mention of how to shut down the core of the device and enter a sleep mode in this design note https://www.altera.com/en_us/pdfs/li...ug_m10_pwr.pdf. However, this power management function does not appear to be a MegaFunction that I can select from Quartus. It looks like custom source code from Altera. So, I will have to download it and see if I can compile it. --- Quote End --- It doesn't look like the MAX10 power management function will reduce the static power consumption of a design with standard CMOS I/Os, except for outputs sourcing current to external loads. The relevant functions are gating of core clocks and shutting IOs with static current consumption like LVDS and SSTL. A previous discussion point has been that tri-stated inputs floating to mid-level can cause additional input buffer power dissipation. You could try if the power consumption of your design decreases if you drive the 'Z' outputs to '0' or '1', or apply clear high or low level externally.