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Valued Contributor III
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MAX10 ADC TSD offset - IO bank 8 voltage?

Hi 

 

I am using a dual-supply MAX10 device with the onboard ADC configured to estimate the FPGA's temperature using the internal TSD. The ADC also estimates board temperature using an analogue TMP36 temperature sensor connected to the dedicated analogue input on the MAX10. The temperature read from the external sensor seems reasonable however the temperature read from the internal sensor is garbage (the offset differs from board to board but is typically reporting 10 - 20 degrees C too low). The ADC is being clocked at 40 MHz from the onboard PLL, which is itself clocked from a 12 MHz source. I have tried disabling all channels except the TSD and this makes no difference and have also tried using a slower ADC clock and internal and external reference options all to no avail. 

 

I have used the ADC with the TSD (and an external analogue temperature sensor) successfully before so I am a bit perplexed that it refuses to work on this board. The only (obvious) significant difference between the two platforms is that on the board that works IO bank 8 is powered from the same 2.5 V supply used for bank 1 and the ADC supplies. On the new board that is misbehaving IO bank 8 is instead powered from a 3.3 V supply. I know that using the ADC places significant usage restrictions on the pins in IO bank 8 (and others) however I have hunted through the documentation with a fine-tooth comb and cannot find anything to suggest that I should not use 3.3 V for bank 8. Have I missed something? (FYI, bank 8 was moved to 3.3 V to make it easier to interface the configuration clear and done signals to a USB interface chip fitted to the new board.) 

 

Thanks in advance 

 

Tim
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Valued Contributor III
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Re: MAX10 ADC TSD offset - IO bank 8 voltage?

Hi, 

 

--- Quote Start ---  

the temperature read from the internal sensor is garbage (the offset differs from board to board but is typically reporting 10 - 20 degrees C too low). The ADC is being clocked at 40 MHz from the onboard PLL, which is itself clocked from a 12 MHz source. I have tried disabling all channels except the TSD and this makes no difference and have also tried using a slower ADC clock and internal and external reference options all to no avail. 

--- Quote End ---  

 

To see huge diffrence in temperature reading, run board for longer time by utilizing most of the FPGA resourceor or by using test setup like ESS or simply using blower. 

 

 

--- Quote Start ---  

cannot find anything to suggest that I should not use 3.3 V for bank 8. Have I missed something? (FYI, bank 8 was moved to 3.3 V to make it easier to interface the configuration clear and done signals to a USB interface chip fitted to the new board.) 

--- Quote End ---  

 

 

It is based on your design kindly check example 3 & 4 in below link. 

https://www.altera.com/en_us/pdfs/literature/dp/max-10/pcg-01018.pdf 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
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Re: MAX10 ADC TSD offset - IO bank 8 voltage?

Hi Anand 

 

Thank you for your quick response. 

 

 

--- Quote Start ---  

To see huge diffrence in temperature reading, run board for longer time by utilizing most of the FPGA resourceor or by using test setup like ESS or simply using blower. 

 

--- Quote End ---  

 

 

The temperature reported responds to freezer spray so I am happy that the result is not stuck - it's just way off. The offset seems to be pretty consistent for each board too; the same firmware in different boards yields different offsets but power-cycling/modifying firmware, eg, changing IP core configurations and rebuilding, on a single development board gives repeatable results. 

 

 

--- Quote Start ---  

It is based on your design kindly check example 3 & 4 in below link. 

https://www.altera.com/en_us/pdfs/literature/dp/max-10/pcg-01018.pdf 

 

--- Quote End ---  

 

 

I believe I have followed the guidelines and our design conforms with example 3. Supplies are shared where possible (with the suggested filters where appropriate) and we are using linear regulators rather than switchers. The supply voltages are as follows: 

 

  • VCC = 1.2V 

  • VCCA = 2.5V 

  • VCCINT = 1.2V (via dedicated ferrite bead + extra decoupling) 

  • VCCD_PLL1 and VCCD_PLL2 = 1.2V (via dedicated ferrite bead + extra decoupling) 

  • VCCA_ADC = 2.5V (via dedicated ferrite bead + extra decoupling) 

  • VCCIOA = 2.5V (via dedicated ferrite bead + extra decoupling) 

  • VCCIOB and VCCIO2 = 2.5V 

  • VCCIO3, VCCIO4, VCCIO5, VCCIO6, VCCIO7 and VCCIO8 = 3.3V 

 

The only significant difference between the power supply configuration on this board and the one that works is that VCCIO8 is now at 3.3V not 2.5V. The tools moan about mixed configuration supply voltages (see post# 57589 (https://alteraforum.com/forum/showthread.php?t=57589)) and indeed continue to moan even though "Force VCCIO to be compatible with configuration I/O voltage" is unchecked in the settings but the device seems to configure reliably. There do not seem to be any warnings about the ADC and it is only the TSD result that is misbehaving. I guess my question is then, is it possible to confirm that VCCIO8 is not used to power any part of the circuitry related to the TSD? 

 

Best regards 

 

Tim
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Beginner
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Re: MAX10 ADC TSD offset - IO bank 8 voltage?

Hi Tim and Anand

 

I am currently having the same problem as described by Tim, where the internal temperature sensor is reporting to low temperature.

 

Before I add more details, did you ever figure out what caused the problem? Were you able to solve it?

 

Best regards

 

Erlend