We have a module connected to the 10M02 CPLD that requires a specific power sequence, many signals from that module are connected to the MAX10. Upon start up we want to first send a start signal from an IO BANK of 3.3V so we want to power on the IO banks that are 3.3V but leave the 1.8V banks unpowered or in tristate until we receive a signal from the module saying it is OK to power on 1.8V. The reason is that the module requires all 1.8V signals to remain off until the module is on, the module is initialized with the start signal from the 3.3V. Do the banks have to be powered on by a certain time interval I can't seem to find this requirement in the datasheet any help would be great.We just want to see if this is possible to do. I noticed that there is a global reset DEVOE but that leaves all output pins in tristate and you cannot select which banks are in tristate. Can we just power on the 3.3V IO bank such as BANK 1 & 8, and leave BANK3, 5 and 6 unpowered until we receive a power good signal from the module? Any help is much appreciated. Thanks in advance..
Hi,Design power sequencing and voltage regulators for the best device reliability—although power sequencing is not required for correct operation, consider the
power-up timing of each rail to prevent problems with long-term device reliability if you are designing a multi-rail powered system. https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_guidelines.pdf Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Delaying an IO bank supply is basically a bad idea, even if the respective bank isn't monitored by POR logic. Instead you want to tristate the respective IO signals in your design and activate it when the required conditions are met.